Generic placeholder image

Nanoscience & Nanotechnology-Asia

Editor-in-Chief

ISSN (Print): 2210-6812
ISSN (Online): 2210-6820

Research Article

Error-aware Design Procedure to Implement Energy-efficient Approximate Squaring Hardware

Author(s): Merin Loukrakpam *, Ch. Lison Singh and Madhuchhanda Choudhury

Volume 10, Issue 4, 2020

Page: [471 - 477] Pages: 7

DOI: 10.2174/2210681209666190807143557

Price: $65

Abstract

Background: In recent years, there has been a high demand for executing digital signal processing and machine learning applications on energy-constrained devices. Squaring is a vital arithmetic operation used in such applications. Hence, improving the energy efficiency of squaring is crucial.

Objective: In this paper, a novel approximation method based on piecewise linear segmentation of the square function is proposed.

Methods: Two-segment, four-segment and eight-segment accurate and energy-efficient 32-bit approximate designs for squaring were implemented using this method. The proposed 2-segment approximate squaring hardware showed 12.5% maximum relative error and delivered up to 55.6% energy saving when compared with state-of-the-art approximate multipliers used for squaring.

Results: The proposed 4-segment hardware achieved a maximum relative error of 3.13% with up to 46.5% energy saving.

Conclusion: The proposed 8-segment design emerged as the most accurate squaring hardware with a maximum relative error of 0.78%. The comparison also revealed that the 8-segment design is the most efficient design in terms of error-area-delay-power product.

Keywords: Approximation, digital system, energy-efficiency, error-resilience, piecewise linear, squaring.

Graphical Abstract
[1]
Sze, V. Designing hardware for machine learning: The important role played by circuit designers. IEEE Solid-State Circuits Magazine, 2017, 9(4), 46-54.
[2]
Mahdiani, H.R.; Ahmadi, A.; Fakhraie, S.M.; Lucas, C. Bio inspired imprecise computational blocks for efficient VLSI implementation of soft-computing applications. IEEE Trans. Circuits Syst. I Regul. Pap., 2010, 57(4), 850-862.
[3]
Venkatesan, R.; Agarwal, A.; Roy, K. MACACO: Modeling and analysis of circuits for approximate computing. Proceedings of the International Conference on Computer-Aided Design, San Jose, CA, USANovember 7-102011.
[4]
Roy, K.; Raghunathan, A. Approximate computing: An energyefficient computing technique for error resilient applications Annual Symposium on VLSI; IEEE Computer SocietyMontpellier, FranceJuly 8-10, 2015
[5]
Mohapatra, D.; Karakonstantis, G.; Roy, K. Signifi-cance driven computation: A voltage-scalable, variation-aware, quality-tuning motion estimator. Proceedings of the 14th IEEE/ACM Int. Symp. Low Power Electron. Design (ISLPED)Avignon, FranceMay 27- 30, 2009
[6]
Chippa, V.K.; Mohapatra, D.; Raghunathan, A.; Roy, K.; Chakradhar, S.T. Scalable effort hardware design: Exploiting algorithmic resilience for energy efficiency. Proceedings of the 47th IEEE/ACM Design Automation Conference, San Francisco, CA, USAJuly 19-23, 2010
[7]
Chanda, M.; Banerjee, S.; Saha, D.; Jain, S. Novel transistor level realization of ultra low power high-speed adiabatic Vedic multiplier. Proceedings of the International Mutli-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s) Kottayam, IndiaMarch 22-23, 2013
[8]
Chang, C.H.; Satzoda, R.K. A low error and high performance multiplexer-based truncated multiplier. IEEE Trans. Very Large Scale Integr. (VLSI). Syst., 2010, 18(12), 1767-1771.
[9]
Kulkarni, P.; Gupta, P.; Ercegovac, M. Trading accuracy for power with an under designed multiplier architecture. Proceedings of the 24th International Conference VLSI Design, Chennai, IndiaJanuary 2-7 2011
[10]
Gupta, V.; Mohapatra, D.; Raghunathan, A.; Roy, K. Low-power digital signal processing using approximate adders. IEEE Trans. Comput. Aided Des. Integrated Circ. Syst., 2013, 32(1), 124-137.
[11]
Narayanamoorthy, S.; Moghaddam, H.A.; Liu, Z.; Park, T.; Kim, N.S. Energy-efficient approximate multiplication for digital signal processing and classification applications. IEEE Trans. Very Large Scale Integr. (VLSI). Syst., 2015, 23(6), 1180-1184.
[12]
Hashemi, S.; Bahar, R.; Reda, S. In: DRUM: A dynamic range unbiased multiplier for approximate applications. Proceedings in IEEE/ACM International Conference Compuuter-Aided Design (ICCAD) Austin, TX, USA November 2-5, 2015.
[13]
Vahdat, S.; Kamal, M.; Afzali-Kusha, A.; Pedram, M. LETAM: A low energy truncation-based approximate multiplier. Comput. Electr. Eng., 2017, 63, 1-7.
[14]
Mitchell, J.N. Computer multiplication and division usi-ng binary logarithms. IRE Trans. Electron. Comput., 1962, 4, 512-517.
[15]
Hall, E.L.; Lynch, D.D.; Dwyer, S.J. Generation of products and quotients using approximate binary logarithms for digital filtering applications. IEEE Trans. Comput., 1970, 100(2), 97-105.
[16]
McLaren, D.J. In: Improved Mitchell-based logarithmic multiplier for low-power DSP applications. Proceedings of the IEEE International [Systems-on-Chip] SOC Conference, Portland, OR, USASeptember 17-20, 2003
[17]
Mahalingam, V.; Ranganathan, N. Improving accuracy in Mitchell’s logarithmic multiplication using operand decomposition. IEEE Trans. Comput., 2006, 55(12), 1523-1535.
[18]
Zendegani, R.; Kamal, M.; Bahadori, M.; Afzali-Kusha, A.; Pedram, M. RoBA multiplier: A rounding-based approximate multiplier for high-speed yet energy-efficient digital signal processing. IEEE Trans. Very Large Scale Integr. (VLSI). Syst., 2017, 25(2), 393-401.
[19]
Ali, H.; Kumar, T.N. On the improved implementations of pre calculated sums of partial products based 7-bit unsigned parallel squarer. Proceedings of the 26th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), Regina, SK, Canada May 5-8. 2013.
[20]
Kunchigi, V.; Kulkarni, L.; Kulkarni, S. Low Power Square and Cube Architectures Using Vedic Sutras. Fifth International Conference on Signal and Image Processing, Bangalore, IndiaJanuary 8-10, 2014
[21]
Gupta, S.D.; Thornton, M.A. A Fixed-point squaring algorithm using an implicit arbitrary radix number system. IEEE J. Emerg. Select. Topics Circuits Systems, 2016, 6(1), 34-43.
[22]
Sethi, K.; Panda, R. Multiplier less high-speed squaring circuit for binary numbers. Int. J. Electron., 2015, 102(3), 433-443.
[23]
Loukrakpam, M.; Lison, Ch.; Choudhury, M. Energy-efficient approximate squaring hardware for error-resilient digital systems. Proceedings of IEEE Electron Device Conference (EDKCON), Kolkata, IndiaNovember 24-25, 2018
[24]
Akbari, O.; Kamal, M.; Afzali-Kusha, A.; Pedram, M. RAP-CLA: A reconfigurable approximate carry look-ahead adder. IEEE Trans. Circuits Syst., II Express Briefs, 2018, 65(8), 1089-1093.

Rights & Permissions Print Cite
© 2024 Bentham Science Publishers | Privacy Policy