Editor(s): Rasit Onur Topaloglu and Peng Li
DOI: 10.2174/97816080507411110101eISBN: 978-1-60805-074-1, 2011ISBN: 978-1-60805-695-8
Indexed in: Scopus, EBSCO.
The last couple of years have been very busy for the semiconductor industry and researchers. The rapid speed of production channel length reduction has brought lithographic challenges to semiconductor modeling. These include stress optimization, transistor reliability and efficient circuit design with respect to interconnects, power and leakage at the chip level. This e-book focuses on the latest semiconductor techniques devised to address these issues. It should be a useful resource for electronic engineers and semiconductor chip designers.
*(Excluding Mailing and Handling)
Personal information is secured with SSL technology