Energy Efficient Configurable Layout of Logic Block in QCA Frame Work for an FPGA

Title:Energy Efficient Configurable Layout of Logic Block in QCA Frame Work for an FPGA

Volume: 13 Issue: 2

Author(s): Arindam Sadhu, Rimpa Dey Sarkar, Kunal Das*, Debashis De and Maitreyi Ray Kanjilal

Affiliation:

• Department of Computer Science, Acharya Prafulla Chandra College (Govt. Sponsored), New Barrackpur, Kolkata 700131,India

Keywords: Field Programmable Gate Array (FPGA), Look-Up Table (LUT), Configurable Logic Block (CLB), Multiplexer (MUX), Demultiplexer (DEMUX), dissipation.

Abstract:

Aims: Embedded system plays a vital role in today’s life. Hence, our interest is in areadelay- energy efficient embedded system design in post-CMOS technology, i.e., QCA.

Objectives: The research is focused on efficient area-delay-energy Configurable Logic Block (CLB) design for Field-Programmable Gate Array architecture (FPGA) with successful simulation-based on next-generation technology, Quantum-dot cellular automata.

Methods: Each proposed circuit is designed on post CMOS 4 dot 2 electron technology, i.e. QCA (Quantum dot Cellular Automata), is adopted in circuit implementation due to low power dissipation, high clock frequency and high package density. QCADesigner is used to verify the functionality of every circuit. QCAPro tool is used for determining power dissipation.

Results: In contrast, a new approach of using de-multiplexer replacing the decoder has been introduced that results in the reduction of the average energy dissipation by almost 57%. A NOR based D flip-flop memory architecture and multiplexer are also used in the lookup table for the configurable logic block. The proposed architecture thus reduces the overall latency. The proposed CLB consists of 6356 QCA cells covering 7.44 um2 area. Write and read latency of proposed CLB are 12 and 7.25 QCA clock, respectively.

Conclusion: The present paper concludes that read and write latency reduction occurs; average energy dissipation, leakage, and switching energy dissipation are reduced in a large amount resulting in an advantage of the overall minimization of the latency for the proposed CLB in the process.

Cite this article as:

Sadhu Arindam , Sarkar Dey Rimpa , Das Kunal *, De Debashis and Kanjilal Ray Maitreyi , Energy Efficient Configurable Layout of Logic Block in QCA Frame Work for an FPGA, Micro and Nanosystems 2021; 13 (2) . https://dx.doi.org/10.2174/1876402912999200602171146