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Micro and Nanosystems

Editor-in-Chief

ISSN (Print): 1876-4029
ISSN (Online): 1876-4037

Research Article

Design of Quantum Cost and Delay Optimized Code Converter Using New Reversible Quantum Circuit Block (QCB)

Author(s): Heranmoy Maity*, Sudipta Banerjee, Raton Mistry, Parna Kundu, Kriti Ojha, Priya Manwani, Barnali Sen, Ishika Verma, Arindam Biswas, Anita Pal and Anup Kumar Bhattacharjee

Volume 13, Issue 1, 2021

Published on: 01 May, 2020

Page: [119 - 123] Pages: 5

DOI: 10.2174/1876402912999200502024055

Price: $65

Abstract

Background: In this article, we have proposed a new reversible quantum circuit block along with the Quantum Cost (QC), Constant Input (CI), Garbage Output (GO) and delay optimized code converter using quantum circuit block.

Methods: Initially, new quantum circuit block has been designed and later reversible code converter circuits have been implemented using it. The proposed new quantum block used to design 2’s complement code converter (2SCCC), cost efficient BCD to Excess-3 Code Converter (BECC) and can also be used to implement different logic functions. The QC of proposed quantum circuit block is 8. The QC and delay of the proposed 2SCCC is 8 and 1 respectively. Similarly, the QC and delay of the proposed BECC is 11 and 2, respectively. The proposed cost efficient BECC is designed using two NOT gate, one Feynman gate and one new quantum circuit block with QC is 11.

Results: The improvement of QC for 2SCCC and BECC is 27.27 % and 21.43%, respectively. The improvement of delay for 2SCCC and BECC are 66.67% and 50%, respectively, compared with respect to the latest reported results.

Conclusion: So the improvement of QC and delay are very high using QCB.

Keywords: Quantum computing, quantum cost, reversible logic gate, delay, garbage output, quantum circuit block.

Graphical Abstract
[1]
Haghparast, M.; Bolhassani, A. Optimized parity preserving quantum reversible full adder/subtractor J. Cir. Sys. Comp., 2016, 14(1650019), 12.
[http://dx.doi.org/10.1142/S0219749916500192]
[2]
Bennett, C.H. Logical reversibility of computation. IBM J. Res. Develop., 1973, 17, 525-532.
[http://dx.doi.org/10.1147/rd.176.0525]
[3]
Maity, H.; Biswas, A.; Bhattacharjee, A.K. Design of QC efficient MOD-8 synchronous UP/DOWN counter using reversible logic gate. Proc. Int. Conf. on Computational Science and Engineering (ICCSE 2016), Kolkata, India2016, pp. 3-6.
[4]
Feynman, R. Quantum mechanical computers. Opt. News, 1985, 11(2), 11-20.
[5]
Peres, A. Reversible logic and quantum computers. Phys. Rev. A Gen. Phys., 1985, 32(6), 3266-3276.
[http://dx.doi.org/10.1103/PhysRevA.32.3266 ]
[6]
Fredkin, E.; Toffoli, T. Conservative logic. Int. J. Theor. Phys., 1982, 21, 219-253.
[http://dx.doi.org/10.1007/BF01857727]
[7]
Maity, H.; Biswas, A.; Bhattacharjee, A.K.; Pal, A. QC optimized design of 4-bit reversible universal shift register using reduced number of logic gate. Inter J. Quant. Info, 2018, 16(1850016), 8.
[8]
Maity, H.; Biswas, A.; Bhattacharjee, A.K.; Pal, A. .Design of quantum cost efficient 4-bit reversible universal shift register. Conf. on Device for Integrated Circuits (DevIC 2017), Kalyani, India, 2017; pp. 44-47..
[9]
Misra, N.K.; Sen, B.; Wairya, S.; Bhoi, B. Testable novel parity-preserving reversible gate and low-cost quantum decoder design in 1d molecular-QCA. J. Circ Syst. Comput., 2017, 26(9)1750145
[http://dx.doi.org/10.1142/S0218126617501456]
[10]
Maity, H.; Biswas, A.; Bhattacharjee, A.K.; Pal, A. Design of Reversible Combinational Circuits Using New Reversible Logic Gate. J. Eng. Sci. Technol. Rev., 2018, 11, 170-172.
[http://dx.doi.org/10.25103/jestr.115.21]
[11]
Misra, N.K.; Sen, B.; Wairya, S. Towards designing efficient reversible binary code converters and a dual-rail checker for emerging nanocircuits. J. Comput. Electron., 2017, 16, 442.
[http://dx.doi.org/10.1007/s10825-017-0960-4]
[12]
Maity, H.; Biswas, A.; Pal, A.; Bhattacharjee, A.K. QC optimized design of reversible 2’s complement code converter. Electron Device Kolkata Conference (2018 IEEE EDKCON), Kolkata, India, 2018; pp. 122-125..
[13]
Maity, H.; Barik, A.K.; Biswas, A.; Bhattacharjee, A.K.; Pal, A. Design of QC, GO and delay optimized BCD to excess-3 and 2’s complement code converter. J. Circ Syst. Comput., 2018, 27(11)1850184
[14]
Shukla, V.; Singh, O.P.; Mishra, G.R.; Tiwari, R.K. Design of a 4- bit 2's complement reversible circuit for arithmetic logic unit applications. Conf. on Communication Computing and Information Technology (ICCCMIT-2012), Chennai, India; 2012, pp. 1-5..
[15]
Misra, N.K.; Wairya, S.; Singh, V.K. Evolution of structure of some binary group based n-bit comparator, n-to-2n decoder by reversible technique. Int. J. VLSI Des. Commun. Syst., 2015, 5, 9-30.
[http://dx.doi.org/10.5121/vlsic.2014.5502]
[16]
Maity, H.; Biswas, A.; Pal, A.; Bhattacharjee, A.K. Design of BCD to excess-3 code converter circuit with optimized QC, GO and CI using reversible gate. Inter J. Quant. Info, 2018, 16(1850061), 5.
[17]
Maity, H.; Banerjee, S.; Biswas, A.; Pal, A.; Bhattacharjee, A.K. Design of reversible shift register using reduced number of logic gate. Micro Nanosyst., 2019, 12, 33-37.
[http://dx.doi.org/10.2174/1876402911666190617112734]
[18]
Haghparast, M.; Hajizadeh, M.; Hajizadeh, R.; Bashiri, R. On the synthesis of different nanometric reversible converters. Middle East J. Sci. Res., 2011, 7, 715-720.
[19]
Kamani, K.; Koneti, S.; Boolampalli, U.; Shankara, S. Energy efficient reversible logic design of code converter. Proc. IEEE International Conference on Green High Performance Computing (ICGHPC), Nagercoil, India2014, pp. 132-136.
[20]
Saravanan, M.; Manic, K.S. Energy efficient code converters using reversible logic gates. Proc. IEEE International Conference on Green High Performance Computing (ICGHPC), Nagercoil, India2013, pp. 1-6.
[http://dx.doi.org/10.1109/ICGHPC.2013.6533921]
[21]
Gandhi, S.M.; Devishree, J.; Venkatesh, J.; Mohan, S.S. Design of reversible circuit for code converter and binary incrementer. Int. J. Info. Technol. Mech. Eng., 2014, 1, 24-33.
[22]
Maity, H.; Biswas, A.; Pal, A.; Bhattacharjee, A.K. The QC optimized design of 2:4 decoder using the new reversible logic block. Micro Nanosyst., 2019, 12(3), 146-148.
[http://dx.doi.org/10.2174/2213476X0666619091614133]

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