PVT Aware Design of a Dead-zone Free High Speed Phase Frequency Detector in 90nm CMOS

Title:PVT Aware Design of a Dead-zone Free High Speed Phase Frequency Detector in 90nm CMOS

Volume: 13 Issue: 4

Author(s): Suraj K. Saw, Madhusudan Maiti, Preetisudha Meher and Alak Majumder*

Affiliation:

• Department of Electronics and Communication Engineering, National Institute of Technology Arunachal Pradesh, Yupia, 791112,India

Keywords: Phase frequency detector, dead zone, lock-in-time, output noise, phase frequency detector, blind zone.

Abstract:

Background & Introduction: With the advent of technology, though the literature highlights many designs of Phase Frequency Detector (PFD), there remains some challenges like area overhead, switching noise near frequency lock point and fast, accurate response to mitigate dead zone and output errors.

Methods: In this article, we have unearthed a low power, high speed and dead zone free PFD, which eliminates the switching noise near that lock-in node. This simple design uses lesser number of transistors to obtain smaller estimated layout area of 0.748mm2 and low power of 496.12μW, when operated at 10 GHz frequency at a power supply of 1.8V in 90nm CMOS technology.

Results: The simulation reads a phase noise and output noise of -113.142dBc/Hz and -180.712dB at 1MHz offset. The circuit not only runs at a frequency as high as 40GHz, but also compatible to be operated at a power supply of as small as 0.9V.

Conclusion: Process Variation analysis performed proves the robustness of the proposed circuit at all process corners. Also, the design gets validated at lower process nodes like 28nm UMC.

Cite this article as:

Saw K. Suraj , Maiti Madhusudan , Meher Preetisudha and Majumder Alak *, PVT Aware Design of a Dead-zone Free High Speed Phase Frequency Detector in 90nm CMOS, Recent Advances in Electrical & Electronic Engineering 2020; 13 (4) . https://dx.doi.org/10.2174/2352096512666190314111752