Abstract
Parasitic capacitance and resistance associated with source/drain silicide contacts are not scaled down, and they have a large influence on the device characteristics considering the scaling effect. The fringe capacitance and source/drain resistance are investigated in this chapter. Futher, the impact of B penetration through gate oxide on threshold voltage is analyzed. As the device is scaled down, the impurities in polycrystalline Si gate tend to penetrate the substrate through the thin gate oxide, and the influence of the penetrated impurity to the shift of threshold voltage becomes significant.
Keywords: Conformal mapping, Effective length, Electric capacitance, Fringe capacitance, Junction depth, Parasitic capacitance, Poisson integration, Resistance, Silicide, SOI, source/drain.
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