Analog Circuit Design for Communication SOC

System Timing Generation: Phase-Locked Loop Design

Author(s): Rong-Jyi Yang

Pp: 64-107 (44)

Doi: 10.2174/978160805037611201010064

* (Excluding Mailing and Handling)


Phase-Locked Loops (PLLs) are widely used in wired/wireless communication systems, disk drive electronics, high-speed digital circuits, and instruments to deal with frequency synthesizing, clock multiplication and synchronization issues. Although the first PLL was realized in 1932 by Bellesize, a French engineer, the broader industrial applications were seen only when the monolithic IC implementation was available in 1965. The characteristic of clock multiplication makes PLLs irreplaceable in modern wireless communication systems. However, the major consideration for the design of a PLL is the stability issue due to the extra pole contributed by the oscillator. Hence the role which PLLs play for clock synchronization in modern IC design is gradually replaced by delay-locked loops (DLLs) in recent years. Due to the difference of their configurations, DLLs are preferred for their unconditional stability and less lock time than PLLs. Additionally, DLLs offer better jitter performance than PLLs do because the noise in the voltage-controlled delay line (VCDL) does not accumulate with time. The other important role for PLLs is the clock/data recovery (CDR) circuit in wired-line communication systems. The CDR circuit was first realized based on a simple PLL with additional devices and is now developed to be an individual category for the phase locking techniques.

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