A dedicated printed electronics technology platform has been developed and implemented. The technology is devoted to the manufacturing of all-organic transistor devices with sub-micron feature size as multilayered structures, obtained through a sequential combination of deposition from solution and patterning steps through stamps. The manufacturing process includes fabrication of both rigid and flexible elastomeric stamps that are used in the development of fully printed devices and circuits on glass and plastic substrates. Moreover, to test the performance of printed electronic devices, a new compact simulation model has been developed taking into account the effect of contact resistance. Such a parameter acts as a key engineering parameter to enable access of polymer-based printed electronics to logic circuits running at relatively high speed, eventually associated with design solutions that allow achieving full rail-to-rail speed-up logic circuits and low power dissipation.