Generic placeholder image

Micro and Nanosystems

Editor-in-Chief

ISSN (Print): 1876-4029
ISSN (Online): 1876-4037

Research Article

Design and Analysis of Novel Non-Reversible & Reversible Parity Generator and Detector in Quantum Cellular Automata using Feynman Gate

Author(s): Neeraj Tripathi, Mohammad Mudakir Fazili* and Rahil Jahangir

Volume 14, Issue 3, 2022

Published on: 26 July, 2021

Page: [256 - 262] Pages: 7

DOI: 10.2174/1876402913666210726170207

Price: $65

Abstract

Aims: A novel design for non-reversible as well as reversible parity generator and detector in Quantum-dot Cellular Automata (QCA) technology is presented in this research article. Parity generator and detector circuits are reliable error-checking components of a nano-communication system.

Objective: The main focus of this research is to design an ultra-low-power fault-tolerant reversible gate implementation of the parity logic function in QCA. An efficient QCA design layout with minimal area, less latency and the least energy dissipation is desired.

Method: The proposed designs are developed using Quantum-dot Cellular Automata (QCA) technology. The circuits are optimized using majority gate reduction and clock zone reduction techniques. Also, the cell-cell interaction technique is employed to further optimize the QCA circuit. To increase the fault tolerance and ultra-low power operation, reversible QCA circuits are designed using cascaded Feynman gates.

Results: The efficiency of the parity generator and detector is calculated to be more than 25% compared to existing QCA layouts. It is demonstrated in this paper that the proposed circuits perform exceptionally well on every design parameter. The design parameters under consideration are cell count, cell area, complexity, crossover count, latency and energy dissipation.

Conclusion: Using reversible logic, a fault-tolerant and defect-sensitive circuit are developed for parity generation and detection.

Keywords: Parity generator, parity detector, nano-communication, fault tolerance, ultra-low power, reversible gate, feynman gate, energy dissipation.

Graphical Abstract
[1]
Mann, C.C. The end of Moore’s law? Technol. Rev., 2000, 103(3), 42-42.
[2]
Sasamal, T.N.; Singh, A.K.; Mohan, A. Quantum-dot cellular automata based digital logic circuits: a design perspective; Springer, 2020.
[http://dx.doi.org/10.1007/978-981-15-1823-2]
[3]
Lent, Craig S. Quantum cellular automata. Nanotechnology, 1993, 49.
[http://dx.doi.org/10.1088/0957-4484/4/1/004]
[4]
Thapliyal, Himanshu; Ranganathan, Nagarajan .; Kotiyal, Saurabh Design of testable reversible sequential circuits. IEEE transactions on very large scale integration (vlsi) systems., 2012, 21, 1201- 1209..
[5]
Mano, M.M.; Ciletti, M. Digital design: with an introduction to the Verilog HDL; Pearson, 2013.
[6]
Teja, V.C.; Polisetti, S.; Kasavajjala, S. QCA based multiplexing of 16 arithmetic & logical subsystems-a paradigm for nano computing., 2008.
[http://dx.doi.org/10.1109/NEMS.2008.4484438]
[7]
Mustafa, M.; Beigh, M. R. Design and implementation of quantum cellular automata based novel parity generator and checker circuits with minimum complexity and cell count., 2013.
[8]
Santra, S.; Roy, U. Design and optimization of parity generator and parity checker based on quantum-dot cellular automata. International Journal of Nuclear and Quantum Engineering, 2014, 8(3), 491-497.
[9]
Ahmad, Firdous; Bhat, G. Novel code converters based on quantum-dot cellular automata (QCA). International Journal of Science and Research; (IJSR), 2014, p. 3.
[10]
Ahmad, F.; Ahmad, P.Z. 2015.2nd International Conference on Computing for Sustainable Global Development (INDIACom),
[11]
Das, J.C.; De, D. Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication. Frontiers of Information Technology & Electronic Engineering, 2016, 17(3), 224-236.
[http://dx.doi.org/10.1631/FITEE.1500079]
[12]
Kumar, D. Design of Practical Parity generator and Parity checker circuits in QCA. 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), 2017,.
[http://dx.doi.org/10.1109/iNIS.2017.16]
[13]
Bahar, Ali Newaz Designing efficient QCA even parity generator circuits with power dissipation analysis. Alexandria engineering journal., 2018, 57, 2475-2484..
[http://dx.doi.org/10.1016/j.aej.2017.02.002]
[14]
Gassoumi, I. An ultra-low power parity generator circuit based on qca technology. J. Electr. Comput. Eng., 2019, 2019.
[http://dx.doi.org/10.1155/2019/1675169]
[15]
Khakpour, M.; Gholami, M.; Naghizadeh, S. Parity generator and digital code converter in QCA nanotechnology. Int. Nano Lett., 2020, 10(1), 49-59.
[http://dx.doi.org/10.1007/s40089-019-00292-8]
[16]
Feynman, R.P. Feynman lectures on computation; CRC Press, 2018.
[http://dx.doi.org/10.1201/9780429500442]
[17]
Bennett, C.H. Logical reversibility of computation. IBM J. Res. Develop., 1973, 17(6), 525-532.
[http://dx.doi.org/10.1147/rd.176.0525]
[18]
Sen, B. Realizing reversible computing in QCA framework resulting in efficient design of testable ALU. ACM J. Emerg. Technol. Comput. Syst., 2014, 11(3), 1-22. [JETC].
[http://dx.doi.org/10.1145/2629538]
[19]
Roohi, A. A parity-preserving reversible QCA gate with self-checking cascadable resiliency. IEEE Trans. Emerg. Top. Comput., 2016, 6(4), 450-459.
[http://dx.doi.org/10.1109/TETC.2016.2593634]
[20]
Torres, F.S. An energy-aware model for the logic synthesis of quantum-dot cellular automata. IEEE Trans. Comput. Aided Des. Integrated Circ. Syst., 2018, 37(12), 3031-3041.
[http://dx.doi.org/10.1109/TCAD.2018.2789782]
[21]
Walus, K. QCADesigner: A rapid design and simulation tool for quantum-dot cellular automata. IEEE Trans. NanoTechnol., 2004, 3(1), 26-31.
[http://dx.doi.org/10.1109/TNANO.2003.820815]
[22]
Timler, John; Lent, Craig S. Power gain and dissipation in quantum- dot cellular automata. journal of applied physics., 2002, 823- 831..
[http://dx.doi.org/10.1063/1.1421217]
[23]
Tougaw, P.D.; Lent, C.S. Dynamic behavior of quantum cellular automata. J. Appl. Phys., 1996, 80(8), 4722-4736.
[http://dx.doi.org/10.1063/1.363455]
[24]
Liu, W. Are QCA cryptographic circuits resistant to power analysis attack? IEEE Trans. NanoTechnol., 2012, 11(6), 1239-1251.
[http://dx.doi.org/10.1109/TNANO.2012.2222663]
[25]
Srivastava, S.; Sarkar, S.; Bhanja, S. Estimation of upper bound of power dissipation in QCA circuits. IEEE Trans. NanoTechnol., 2008, 8(1), 116-127.
[http://dx.doi.org/10.1109/TNANO.2008.2005408]
[26]
Ma, X.; Huang, J.; Lombardi, F. A model for computing and energy dissipation of molecular QCA devices and circuits. ACM J. Emerg. Technol. Comput. Syst., 2008, 3(4), 1-30. [JETC
[http://dx.doi.org/10.1145/1324177.1324180]
[27]
Srivastava, S.; Asthana, A.; Bhanja, S.; Sarkar, S. QCAPro-an error-power estimation tool for QCA circuit design. 2011 IEEE international symposium of circuits and systems; (ISCAS), 2011, pp. 2377-2380.
[http://dx.doi.org/10.1109/ISCAS.2011.5938081]

Rights & Permissions Print Cite
© 2024 Bentham Science Publishers | Privacy Policy