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ISSN (Print): 2352-0965
ISSN (Online): 2352-0973

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General Research Article

Suppression of Timing Variations due to Random Dopant Fluctuation by Back-gate Bias in a Nanometer CMOS Inverter

Author(s): Kai Zhang, Weifeng Lu*, Peng Si, Zhifeng Zhao and Tianyu Yu

Volume 14, Issue 3, 2021

Published on: 08 December, 2020

Page: [339 - 346] Pages: 8

DOI: 10.2174/2352096513666201208102615

Price: $65

Abstract

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits.

Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology.

Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG.

Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover they are also insensitive to channel doping with back-gate bias.

Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

Keywords: Nanometer CMOS, timing characteristic, back-gate bias, random dopant fluctuation, CMOS inverter, RDF-induced timing.

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