Galois Field Inversion/Division Using Multiple-Valued Logic

Author(s): Nabil Abu-Khader, Pepe Siy

Journal Name: Recent Patents on Electrical Engineering
Continued as Recent Patents on Electrical & Electronic Engineering

Volume 1 , Issue 3 , 2008


We present a pipelined inversion/division circuit in Galois field using AB2 circuit technique (where both A and B are elements in the finite field). We use composite Galois fields in a multiple-valued logic (MVL) approach to minimize the inversion/division circuit needed for binary Galois fields. The overall design, which connects basic cells in a systolic manner, thereby making effective use of pipelining, is shown. The fact that less literals are used speeds up the calculation operation. Also, our circuit shows a significant amount of savings in both transistor count and connections, which is so important in VLSI. In this review important patents are also discussed.

Keywords: MVL, galois field, inversion/division

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Article Details

Year: 2008
Published on: 01 March, 2012
Page: [231 - 237]
Pages: 7
DOI: 10.2174/1874476110801030231
Price: $65

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