Gate Diffusion Input Based 10-T CNTFET Power Efficient Full Adder

(E-pub Ahead of Print)

Author(s): Priyanka Tyagi*, Sanjay Kumar Singh, Piyush Dua

Journal Name: Recent Advances in Electrical & Electronic Engineering
Formerly Recent Patents on Electrical & Electronic Engineering


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Abstract:

Background: Full adder is the key element of the digital electronics. The CNTFET is the most promising device in modern electronics. To enhance the performance of the full adder CNTFET is used in place of the CMOS.

Objective: To implement the high speed full adder circuit for advance applications of the digital world.

Methods: Full adder circuit with new Gate diffusion technique has been implemented in this work. There is the comparative study of the 10-T CNTFET full adder with GDI technique and the 10-T Finfet based full adder using GDI technique. Ultralow power feature is the additional advantage of the GDI technique. This technology provides the full swing voltage to the circuit moreover it also reduces number of transistors required. This technique has been used with CNTFET to upgrade full adder in terms of the dissipated power and product of power consumed and delay introduced in the circuit.

Results: The proposed design shows that the low power dissipation comes out to be approximately 4.3nW at 0.5volts. The power delay product is 4.7x10-20 J at the same voltage level. The Finfet design also shows the better performance with GDI. But GDI enhance CNTFET based design power consumption about 32% from the FinFET.

Conclusions: CNTFET observed the better response due to good current conductivity as compare to the FinFET. This work has been implemented and simulated on the 32nm node technology.

Keywords: Gate diffusion input, CNTFET, CMOS, FinFET, PDP, GDI technique.

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Article Details

(E-pub Ahead of Print)
DOI: 10.2174/2352096514666210106094136
Price: $95