Introduction: Here, we present an n-channel cylindrical gate tunnel FET with drain
underlap engineering (CGT-DU) and the simulation process is carried out using a 3-D device
simulator from Synopsys.
Methods: The analog and radio frequency (RF) performance of the device has been studied
extensively in terms of the electric field, energy band analysis, drain current, gain bandwidth
product, unity gain cut-off frequency, transconductance frequency product, and maximum
oscillation frequency for different values of drain underlap length.
Results: The increase in underlap length in CGT paves the way for a substantial reduction in
ambipolar current without degrading the ON-state current. The proposed device exhibits lower
lateral electric field, larger tunneling length and lower gate to drain capacitance at the drain end
with a higher underlap length.
Conclusion: CGT-DU exhibits superior ambipolar and RF performance without degrading ONstate
current and threshold voltage.