Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

Author(s): Sai Venkatramana Prasada G.S*, G. Seshikala, S. Niranjana

Journal Name: Recent Advances in Electrical & Electronic Engineering
Formerly Recent Patents on Electrical & Electronic Engineering

Volume 13 , Issue 6 , 2020

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Graphical Abstract:


Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs.

Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology.

Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio.

Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

Keywords: DSP, full adder, mentor graphics, multiplier, PDP, VLSI, W/L aspect ratio.

R. Dhayabarani, and R.S.D. Wahida Banu, "Performance analysis of multiplier using full adder", Int. J. Adv. Eng. Nano Technol., (IJAENT), , vol. 1, no. 3, . pp. 5-8, February 2014
D. Garg, and M.K. Rai, "CMOS based 1-bit full adder cell for low-power delay product", IJECCT, vol. 2, no. 4, pp. 18-23, 2012.
D. Sandhu, S. Singh, and S. Singh, "Analysis of CMOS full adder circuits for low voltage VLSI design, Int. J. Comput. Sci. Commun. Eng.,(IJCSCE) Special issue on “Rec. Adv. Eng. Technol.” NCRAET, pp. 107-113",
S. Mishra, S.S. Tomar, and S. Akashe, Design Low Power 10T Full adder Using Process and Circuit Techniques , 2012, .
K. Nehru, A. Shanmugam, and S. Vadivel, "“CLRCL full adder based low power multiplier architectures”, ISSN: 2249 – 6559", Int. J. VLSI Embedded Syst. IJVES, vol. 03, no. 01, pp. 107-112, 2012.
D. Kudithipudi, and E. John, "Implementation of low power digital multipliers using 10 transistor adder blocks", J. Low Power Electron., vol. 1, pp. 1-11, 2005.
A. Saradindu Panda, and A. Banerjee, B. Maji, and A.K. Mukhopadhyay, "Power and delay comparison in between different types of full adder circuits, Int. J. Adv. Res. Electric", Electron. Instrumentat. Eng., vol. 1, no. 3, pp. 168-172, 2012.
S. Murugeswari, and S.K. Mohideen, "Design of area efficient and low power multipliers using multiplexer based full adder", IEEE Conference Number - 33344, 2nd International Conference on Current Trends in Engineering and Technology, .ICCTET’: Coimbatore, India,, pp. 388-392.July 2014,
R. Saravanan, M. Kalaiyarasi, S. Jim Hawkinson, and D. Sathya, Evaluation of Power Delay Product for Low Powe Full Adder Circuits based on GDI Logic Cell using Mentor Graphics , 2014.
S. Khan, S. Kakde, and Y. Suryawanshi, "Multiplier using energy efficient CMOS full adder", Int. Conf. Computat. Intell. Comput. Res.. 2013
K. Reddy, "Low power-area designs of 1bit full adder in cadence virtuoso Platform", Int. J. VLSI Des. Commun. Syst. (VLSICS), vol. 4, no. 4, pp. 55-64, 2013.
P.V. Rao, P.C.P. Raj, and S. Ravi, In: IEEE Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2009, pp. 1354-1357.

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Article Details

Year: 2020
Page: [864 - 870]
Pages: 7
DOI: 10.2174/2352096513666200107091932
Price: $25

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