R. Dhayabarani, and R.S.D. Wahida Banu, "Performance analysis of multiplier using full adder", Int. J. Adv. Eng. Nano Technol.,
(IJAENT), , vol. 1, no. 3, . pp. 5-8, February 2014
D. Garg, and M.K. Rai, "CMOS based 1-bit full adder cell for low-power delay product", IJECCT, vol. 2, no. 4, pp. 18-23, 2012.
D. Sandhu, S. Singh, and S. Singh, "Analysis of CMOS full adder circuits for low voltage VLSI design, Int. J. Comput. Sci. Commun. Eng.,(IJCSCE) Special issue on “Rec. Adv. Eng. Technol.” NCRAET, pp. 107-113",
S. Mishra, S.S. Tomar, and S. Akashe, Design Low Power 10T Full adder Using Process and Circuit Techniques , 2012, .
K. Nehru, A. Shanmugam, and S. Vadivel, "“CLRCL full adder based low power multiplier architectures”, ISSN: 2249 – 6559", Int. J. VLSI Embedded Syst. IJVES, vol. 03, no. 01, pp. 107-112, 2012.
A. Saradindu Panda, and A. Banerjee, B. Maji, and A.K. Mukhopadhyay, "Power and delay comparison in between different types of full adder circuits, Int. J. Adv. Res. Electric", Electron. Instrumentat. Eng., vol. 1, no. 3, pp. 168-172, 2012.
S. Murugeswari, and S.K. Mohideen, "Design of area efficient and low power multipliers using multiplexer based full adder", IEEE Conference Number - 33344, 2nd International Conference on Current Trends in Engineering and Technology, .ICCTET’: Coimbatore, India,, pp. 388-392.July 2014,
R. Saravanan, M. Kalaiyarasi, S. Jim Hawkinson, and D. Sathya, Evaluation of Power Delay Product for Low Powe Full Adder Circuits based on GDI Logic Cell using Mentor Graphics , 2014.
K. Reddy, "Low power-area designs of 1bit full adder in cadence virtuoso Platform", Int. J. VLSI Des. Commun. Syst. (VLSICS), vol. 4, no. 4, pp. 55-64, 2013.
P.V. Rao, P.C.P. Raj, and S. Ravi, In: IEEE Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2009, pp. 1354-1357.