Performance Comparison of InAs Based DG-MOSFET with Respect to SiO2 and Gate Stack Configuration

Author(s): Sanjit K. Swain*, Sudhansu M. Biswal, Satish K. Das, Sarosij Adak, Biswajit Baral

Journal Name: Nanoscience & Nanotechnology-Asia

Volume 10 , Issue 4 , 2020

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Graphical Abstract:


Objective: In this proposed work, the Analog, RF and Linearity performances of a DGMOSFET have been analyzed by considering InAs as a channel material.

Methods: For the very first time, gate stack techniques in this device have been incorporated and a comparative analysis is conducted with respect to SiO2 oxide layer. The variations in different patterns of oxide layer and their comparison have been thoroughly investigated to have a better understanding of various performance parameters. A thorough analysis of the key figure-of-merits such as trans-conductance factor, transconductance generation factor (TGF), gate capacitance, cutoff frequency (fT), maximum frequency of oscillation (fmax), GBW and various linearity parameters such as gm2, gm3,VIP2, VIP3, IIP3, has been studied with respect to SiO2 oxide material and gate stack technology.

Result: The simulation results revealed that the performances of the device are sensitive to both the oxide materials and it was also inferred that gate stack technology gave a better performance over SiO2 oxide layer.

Conclusion: These results have significant effects in analog, RF and linearity operations. In this work, computer aided design (TCAD) simulations by 2D ATLAS, Silvaco International have been used.

Keywords: Gate stack, InAs channel, analog applications, RF applications, linearity behavior, ATLAS.

Wang, R.; Zhuge, J.; Huang, R.; Tian, Y.; Xiao, H.; Zhang, L.; Li, C.; Zhang, X.; Wang, Y. Analog/RF performance of Si nanowire MOSFETS and the impact of process Vaiation. IEEE Trans. Electron Dev., 2007, 54(6), 1288-1294.
Taur, Y.; Buchanan, D.A.; Chan, W.; Frank, D.J.; Ismil, K.E.; Lo, S.H.; Sai-Halasz, G.A.; Viswanathan, R.G.; Wann, H.J.C.; Wong, S.J. CMOS scaling into the nanometer regime. Proc. IEEE, 1997, 85, 486.
Datta, S. Recent advances in high performance CMOS transistors: From planar to non-planar. Electrochem. Soc. Interface, 2013, 22, 41.
Tridevi, N.; Kumar, M.; Haldar, S.; Deswal, S.S.; Gupta, M.; Gupta, R.S. Analytical modeling of junctionless accumulation mode MOSFET (JAM-CSG). Num. Modell., 2016, 29(6), 1036-1043.
Coquand, R. Strain-induced performance enhancement of tri-gate and omega-gate nanowire FETs scaled down to 10 nm width, IEEE, Symposiun on VLSI Technology Digest of Technical Papers , 2012; pp. 13-14.
Anwar, A.; Hossain, I. A comparative numerical simulation of a nanoscaled body on insulator FinFET. Proceedings of the 27th International Conference on MicroelectronicsNis, Serbia,May 16- 19, 2010
Song, Y.J.; Choi, W.Y.; Park, J.H.; Lee, J.D.; Park, B.G. Design optimization of Gate-All-Around (GAA)MOSFETs. Proceedings of the IEEE Transac. Nanotechnology, 2010, 5(3), 186-191.
Park, J.T.; Colinge, J-P.; Diaz, C.H. Pi-Gate SOI MOSFET. IEEE Electron Device Lett., 2001, 22(8), 405-406.
Lee, C-W. Performance estimation of Junctionlessmultigatetransistors. Solid-State Electron., 2009, 54, 97-103.
Gundapaneni, S.; Baraj, M.; Pandey, R.K.; Murai, K.V.R.; Ganguly, S.; Kottanthravil, A. Effect of band to band tunneling on junctionlesstransistors. IEEE Trans. Electron Dev., 2012, 59(4), 1023-1029.
Baruah, R.K.; Paili, R.P. Analog performance of bulk planar junction-lesstransistor. Proceedings of the ICCCNT IEEE International Conference, Coimbatore, India, July 26-28, 2012
Sallese, J.M.; Chevillon, N.; Lallement, C.; Iniguez, B.; Pregaldiny, F. Charge–based modeling of junction-less double-gate field-effect transistors. IEEE Trans. Electron Dev., 2011, 58, 2658-2637.
Choi, S.-J.; Moon, D.-I.; Kim, S.; Duarte, J.; Choi, Y.K. Sensitivity of threshold voltage to nanowire width variation in junctionlesstransistors. IEEE Electron Device Lett., 2011, 32(-2), 125-127.
Wang, T.; Lou, L.; Lee, C. A junctionless gate-all-around silicon nanowire FET of high linearity and its potential applications. IEEE electron Dev. Lett., 2013, 34(4), 478-480.
Lee, S.M. A comparative study on hot carrier effects in inversion-mode and junctionless MUGFETs. Solid-State Electron., 2013, 79, 253-257.
Lee, C.W. Slope in junction-less multigate transistors. Appl. Phys. Lett., 2009, 94(5), 511-512.
Lee, C-J.; Tsai, T-I.; Liou, Y-L.; Lin, Z-M.; Lin, H-C.; Chao, T-S. Gate all around junction-less Multiplegate Transistors with heavily doped polysilicon nanowire channels. IEEE Electron Device Lett., 2011, 32(4), 521-523.
Colinge, J.P. From gate–all-around to nanowire MOSFETs. Proceedings of Semiconductor Conference, Sinaia, Romania15 October-17 September 2007
Swain, S.K.; Adak, S.; Sharma, B.; Pati, S.K.; Sarkar, C.K. Effect of channel thickness and doping concentration on sub-threshold performance of graded channel and gate stack DG MOSFETs. J. Low Power Electron., 2015, 11, 1-7.
Swain, S.K.; Dutta, A.; Adak, S.; Pati, S.K.; Sarkar, C.K. Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DG- MOSFETs. Microelectron. Reliabil. (Elsevier), 2016, 61, 24-29.
Adak, S.; Swain, S.K.; Dutta, A.; Rahaman, H.; Sarkar, C.K. Influence of channel length and high-K oxide thickness on subthreshold DC performance of graded channel and gate stack DG MOSFETsNANO. In: Brief Reports and Reviews; World Scientific Publishing Company: Singapore, 2016.
Device simulator ATLAS user manual. Silvaco int., Santa Clara, CA Available from: (Accessed on: January 01, 2016)
Kaya, S.; Ma, W. Optimization of RF linearity in DG-MOSFETs. IEEE Electron Device Lett., 2004, 25, 308-310.

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Article Details

Year: 2020
Published on: 25 August, 2020
Page: [419 - 424]
Pages: 6
DOI: 10.2174/2210681209666190919094434
Price: $25

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