Novel Self-Pipelining Approach for Speed-Power Efficient Reliable Binary Multiplication

Author(s): Aloke Saha*, Rahul Pal, Jayanta Ghosh

Journal Name: Micro and Nanosystems

Volume 12 , Issue 3 , 2020

Become EABM
Become Reviewer
Call for Editor

Graphical Abstract:


Background: The present study explores a novel self-pipelining strategy that can enhance speed-power efficiency as well as the reliability of a binary multiplier as compared to state-of-art register and wavepipelining.

Method: Proper synchronization with efficient clocking between the subsequent self-pipelining stages has been assured to design a self-pipelined multiplier. Each self-pipelining stage consists of self-latching leaf cells that are designed, optimized and evaluated by TSMC 0.18μm CMOS technology with 1.8V supply rail and at 25°C temperature. The T-Spice transient response and simulated results for the designed circuits are presented. The proposed idea has been applied to design 4-b×4-b self-pipelined Wallace- tree multiplier. The multiplier was validated for all possible test patterns and the transient response was evaluated. The circuit performance in terms of propagation delay, average power and Power-Delay- Product (PDP) is recorded. Next, the decomposition logic is applied to design a higher-order multiplier (i.e., 8-bit×8-bit and 16-bit×16-bit) based on the proposed strategy using 4-bit×4-bit self-pipelined multiplier. The designed multiplier was also validated through extensive TSpice simulation for all the required test patterns using W-Edit and the evaluated performance is presented. All the designs, optimizations and evaluations performed are based on BSIM3 device parameter of TSMC 0.18μm CMOS technology with 1.8V supply rail at 25°C temperature using S-Edit of Tanner EDA.

Results: The reliability was investigated of the proposed 4-b×4-b multiplier in the temperature range - 40°C to 100°C for maximum PDP variation.

Conclusion: A benchmarking analysis in terms of speed-power performance with recent competitive design reveals preeminence of the proposed technique.

Keywords: Decomposition logic, Power-Delay-Product (PDP), reliability, self-latching, self-pipelining, parallel multiplier.

Saha, A.; Kumar, S.; Das, D.; Chakraborty, M. LP-HS logic evaluation on TSMC 0.18 µm CMOS technology. Int. J. High Speed Electron. Syst. (IJHSES), 2017, 26(4), 1740024.
Jamshidi, V.; Fazeli, M. Design of ultra-low power current mode logic gates using magnetic cells. Int. J. Electron. Commerce, 2018, 83, 270-279.
Gupta, R.; Gupta, R.; Sharma, S. Design of high speed and low power 4-bit comparator using FGMOS. Int. J. Electron. Commerce, 2017, 76, 125-131.
Saha, A.; Pal, R.; Naik, A.G.; Pal, D. Novel CMOS multi-bit counter for speed-power optimization in multiplier design. Int. J. Electron. Comm. (IJEC), 2018, 95, 189-198.
Zhang, Z.; He, Y. A low error energy-efficient fixed-width booth multiplier with sign-digit-based conditional probability estimation. IEEE Trans. Circ. Syst. II: Exp. Briefs, 2018, 65(2), 236-240.
Liu, W.; Cao, T.; Yin, P.; Zhu, Y.; Wang, C.; Swartzlander, E.E.; Lombardi, F. Design and analysis of approximate redundant binary multipliers. IEEE Trans. Comput., 2018, 68(6), 804-819.
Ding, J.; Li, S. A modular multiplier implemented with truncated multiplication. IEEE Trans. Circ. Syst. II: Exp. Briefs, 2018, 65(11), 1713-1717.
Venkatachalam, S.; Ko, S-B. Design of power and area efficient approximate multipliers. IEEE Trans. VLSI Systems, 2017, 25(5), 1782-1786.
Ha, M.; Lee, S. Multipliers with approximate 4-2 compressors and error recovery modules. IEEE Embed. Syst. Lett., 2018, 10(1), 6-9.
Xue, H.; Patel, R.; Boppana, N.V.V.K.; Ren, S. Low-power-delay-product radix-4 8*8 booth multiplier in CMOS. IET Electron. Letter, 2018, 54(6), 344-346.
Antelo, E.; Montuschi, P.; Nannaarelli, A. Improved 64-bit radix-16 booth multiplier based on partial product array height reduction. IEEE Trans. Circuits Syst. I Regul. Pap., 2017, 64(2), 409-418.
Saha, A. Pal, D.; Chandra, M. Low power 6-GHz wave-pipelined 8b×8b multiplier. IET Circuits Dev. Syst., 2013, 7(3), 124-140.
Saha, A. Pal, D.; Chandra, M. Benchmarking of DPL based 8b×8b novel wave-pipelined multiplier. Int. J. Electron. Lett. (IJEL),, 2017, 5(1), 115-128.
Gomes, S.V.; Sasipriya, P.; Bhaaskaran, V.S.K. A low power multiplier using a 24-transistor latch-adder. Indian J. Sci. Technol., 2015, 8(19), 1-5.
Lin, J-F. Low power latch-adder based multiplier design. J. Semicond. Technol. Sci., 2017, 17(6), 806-814.
Ing-Chao, L.; Yu-Hung, C.; Yi-Ming, Y. aging-aware reliable multiplier design with adaptive hold logic. IEEE Trans. VLSI Systems, 2014, 23(3), 544-556.
Wey, I.C.; Peng, C.C.; Liao, F.Y. Reliable low-power multiplier design using fixed-width replica redundancy block. IEEE Trans. VLSI Systems, 2014, 23(1), 78-87.
Saha, A.; Pal, D. Novel high speed MCML 8-bit by 8-bit multiplier. IEEE International Conference on Devices & Communications (ICDeCom-11), BIT Mesra, India, , 2011; pp. 1-5.
Ramanathan, P.; Vanathi, P.T.; Agarwal, S. High speed multiplier design using decomposition logic. Serb. J. Elect. Eng., 2009, 6(1), 33-42.
Asif, S.; Kong, Y. Design of an algorithmic Wallace multiplier using high speed counters Tenth International Conference on Com158 Micro and Nanosystems, 2020, Vol. 12, No. 3 Saha et al. puter Engineering & Systems (ICCES), 2015.
Kuo, T-Y.; Wang, J-S. A low-voltage latch-adder based tree multiplier. IEEE International Symposium on Circuits and Systems (ISCAS 2008), , pp. 804-807.Seattle, WA, USA2008
Wallace, C.S. A suggestion for a fast multiplier. IEEE Trans. Electron. Comput., 1964, EC-13(1), 14-17.
Dadda, L. Some schemes for parallel multipliers. Alta Freq., 1965, 34, 349-356.
Saha, A.; Pal, D. DPL-based novel binary-to-ternary converter on CMOS technology. AEU Int. J. Electron. Commun., 2018, 92, 69-73.
Burleson, W.P.; Ciesielski, M.; Klass, F.; Liu, W. Wave-pipelining: a tutorial and research survey. IEEE Trans. (VLSI). Systems, 1998, 6(3), 464-474.
Weste, N.H.E.; Harris, D.M. CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed; Pearson Education: London, UK, 2011, pp. 670-671.

open access plus

Rights & PermissionsPrintExport Cite as

Article Details

Year: 2020
Published on: 16 September, 2019
Page: [149 - 158]
Pages: 10
DOI: 10.2174/1876402911666190916155445

Article Metrics

PDF: 20