Analytical Modeling of D.C. Parameters of Double Gate Junctionless MOSFET in Near and Subthreshold Regime for RF Circuit Application

Author(s): Dipanjan Sen*, Savio J. Sengupta, Swarnil Roy, Manash Chanda, Subir K. Sarkar

Journal Name: Nanoscience & Nanotechnology-Asia

Volume 10 , Issue 4 , 2020

Become EABM
Become Reviewer
Call for Editor

Graphical Abstract:


Aims: In this work, a Junction-Less Double Gate MOSFET (JLDG MOSFET) based CMOS inverter circuit is proposed for ultra-low power applications in the near and sub-threshold regime operations.

Background: D.C. performances like power, delay and voltage swing of the proposed Inverter have been modeled analytically and analyzed in depth. JLDG MOSFET has promising features to reduce the short-channel effects compared to the planner MOSFET because of better gate control mechanism. So, proposed Inverter would be efficacious to offer less power dissipation and higher speed.

Objective: Impact of supply voltage, temperature, High-k gate oxide, TOX, TSI on the power, delay and voltage swing of the Inverter circuits have been detailed here.

Methods: Extensive simulations using SILVACO ATLAS have been done to validate the proposed logic based digital circuits. Besides, the optimum supply voltage has been modelled and verified through simulation for low voltage operations. In depth analysis of voltage swing is added to measure the noise immunity of the proposed logic based circuits in Sub & Near-threshold operations. For ultra-low power operation, JLDG MOSFET can be an alternative compared to conventional planar MOSFET.

Results: Hence, the analytical model of delay, power dissipation and voltage swing have been proposed of the proposed logic based circuits. Besides, the ultra-low power JLDG CMOS inverter can be an alternative in saving energy, reduction of power consumption for RFID circuit design where the frequency range is a dominant factor.

Conclusion: The power consumption can be lowered in case of UHF, HF etc. RF circuits using the Double Gate Junction-less MOSFET as a device for circuit design.

Keywords: Junction-less double gate MOSFET, CMOS-inverter, power-delay product, voltage swing, RF application, D.C. parameters.

Rabaey, J. Ultra-low-power design—The roadmap to disappearing electronics and ambient intelligence. IEEE Circuits Dev. Mag, 2006, 44, 23-29.
Mohapatrad, S.K.; Pradhand, K.P.; Sahu, P.K. Some device design considerations to enhance the performance of DG-MOSFETs. Transac. Elect. Electron. Mater, 2013, 14(6), 291-294.
Chanda, M.; De, S.; Sarkar, C.K. Modeling of characteristic parameters for nano-scale junctionless double gate MOSFET considering quantum mechanical effect. J. Comput. Electron., 2014, 14(1), 262-269.
Dhiman, G.; Pourush, R.; Ghosh, P.K. Performance analysis of high-κ material gate stack based nanoscale junction less double gate MOSFET. Mater. Focus, 2018, 7(2), 259-267.
Abhinav and S. Rai. Reliability analysis of Junction-less Double Gate (JLDG) MOSFET for analog/RF circuits for high linearity applications. Microelectronics J., 2017, 64, 60-68.
Jazaeri, F.; Barbut, L.; Koukab, A.; Sallese, J-M. Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime. Solid-State Electron., 2013, 82, 103-110.
Gnudi, A.; Reggiani, S.; Gnani, E.; Baccarani, G. Semianalytical model of the subthreshold current in short-channel junctionless symmetric double-gate field-effect transistors. IEEE Trans. Electron Dev., 2013, 60(4), 1342-1348.
SILVACO International 2000,. ATLAS: 2-D Device Simulation Software.
Arora, N.D.; Hauser, J.R.; Roulston, D.J. Electron and hole mobilities in silicon as a function of concentration and temperature. IEEE Trans. Electron Dev., 1982, 29(2), 292-295.
Fossum, J.G.; Lee, D.S. A physical model for the dependence of carrier lifetime on doping density in nondegenerate silicon. Solid-State Electron., 1982, 25, 741-747.
Saha, S. MOSFET test structures for two-dimensional device simulation, Solid State Electron. Solid-State Electron., 2013, 38(1), 69-73.
Mohapatra, K.; Pradhan, P.; Sahu, P.K. Influence of high-k gate dielectric on nanoscale DG-MOSFET. Int. J. Adv. Sci. Technol., 2014, 65, 19-26.
Roy, N.C.; Gupta, A.; Rai, S. Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra low-power analog/RF circuits. Microelectronics J., 2015, 46(10), 916-922.
Ghosh, D.; Parihar, M.S.; Armstrong, G.A.; Kranti, A. High- performance junctionless MOSFETs for ultralow-power analog/RF applications. IEEE Electron Device Lett., 2012, 33(10), 1477-1479.
Jazaeri, F.; Barbut, L.; Sallese, J.M. Modeling and design space of junctionless symmetric DGMOSFETs with long channel. IEEE Trans. Electron Dev., 2013, 60(7), 2120-2127.
Doria, R.T. Junctionless multiple-gate transistors for analog applications. IEEE Trans. Electron Dev., 2011, 58(8), 2511-2519.
Tsividis, Y. Mixed analog digital vlsi devices and technology, 1st Edition; World Scientific Publishing Co. Pvt. Ltd: Singapore, 2005.
Alioto, M. Closed-form analysis of DC noise immunity in subthreshold CMOS logic circuits. Proceedings of 2010 IEEE International Symposium on Circuits and Systems, Paris, France30 May-2 June, 2010
Chakraborty, A.S.; Chanda, M.; Sarkar, C.K. Analysis of noise margin of CMOS inverter in sub-threshold regime. Proceedings of the Students Conference on Engineering and Systems (SCES), Allahabad, India April 12-14, 2013

Rights & PermissionsPrintExport Cite as

Article Details

Year: 2020
Published on: 25 August, 2020
Page: [457 - 470]
Pages: 14
DOI: 10.2174/2210681209666190730170031
Price: $25

Article Metrics

PDF: 14