Aims: In this work, a Junction-Less Double Gate MOSFET (JLDG MOSFET) based
CMOS inverter circuit is proposed for ultra-low power applications in the near and sub-threshold
Background: D.C. performances like power, delay and voltage swing of the proposed Inverter
have been modeled analytically and analyzed in depth. JLDG MOSFET has promising features to
reduce the short-channel effects compared to the planner MOSFET because of better gate control
mechanism. So, proposed Inverter would be efficacious to offer less power dissipation and higher
Objective: Impact of supply voltage, temperature, High-k gate oxide, TOX, TSI on the power,
delay and voltage swing of the Inverter circuits have been detailed here.
Methods: Extensive simulations using SILVACO ATLAS have been done to validate the proposed
logic based digital circuits. Besides, the optimum supply voltage has been modelled and verified
through simulation for low voltage operations. In depth analysis of voltage swing is added to
measure the noise immunity of the proposed logic based circuits in Sub & Near-threshold operations.
For ultra-low power operation, JLDG MOSFET can be an alternative compared to conventional
Results: Hence, the analytical model of delay, power dissipation and voltage swing have been proposed
of the proposed logic based circuits. Besides, the ultra-low power JLDG CMOS inverter can
be an alternative in saving energy, reduction of power consumption for RFID circuit design where
the frequency range is a dominant factor.
Conclusion: The power consumption can be lowered in case of UHF, HF etc. RF circuits using the
Double Gate Junction-less MOSFET as a device for circuit design.