Improved Domino Logic Circuits and its Application in Wide Fan-In OR Gates

Author(s): Deepika Bansal*, Bal Chand Nagar, Brahamdeo Prasad Singh, Ajay Kumar

Journal Name: Micro and Nanosystems

Volume 12 , Issue 1 , 2020

Become EABM
Become Reviewer

Graphical Abstract:


Background: Main concern in efficient VLSI circuit designing is low-power consumption, high-speed and noise tolerance capability.

Objective: In this paper, two efficient and high-performance topologies are proposed for cascaded domino logic using carbon nanotube MOSFETs (CN-MOSFETs). The first topology is designed to remove the intermediate charge sharing problem without any keeper circuit, whereas the second one holds the true logic level of the evaluation phase without any voltage drop for next precharge phase. The proposed topologies are suitable for cascading of the high-performance domino circuits.

Methods: The proposed domino circuits are tested and verified using Synopsys HSPICE simulator with 32nm CN-MOSFET technology provided by Stanford University.

Conclusion: The power delay product of proposed DL-I and DL-II improves by 32.59 % and 40.98 % for 8-input OR gate as compared to standard logic respectively at the clock frequency of 500 MHz. The simulation results validate that the proposed circuits improve the performance of pseudo domino logic with respect to leakage power consumption, delay and unity noise gain.

Keywords: Dynamic logic, carbon nano-tubes, CN-MOSFET, keeper, stack, charge sharing.

Kang, S.M.; Leblebici, Y. CMOS Digital Integrated Circuits: Analysis and Design; Tata McGraw-Hill Publishing company Ltd:New Delhi,. , 2007.
Sun, Y.; Kursun, V. N-type carbon-nanotube MOSFET device profile optimization for very large scale integration. Trans. Electr. Electr. Mater., 2011, 12, 43-50.
Beaumont, A.; Dubuc, C.; Beauvais, J.; Drouin, D. Room temperature single-electron transistor featuring gate-enhanced on-state current. IEEE Electron Device Lett., 2009, 30, 766-768.
Tougaw, P.D.; Lent, C.S. Logical devices implemented using quantum cellular automatax. J. Appl. Phys., 1994, 75, 1818-1825.
Rabaey, J.M.; Chandrakasan, B.; Nicolic, B. Digital Integrated Circuits: A Design Perspective; Pearson Education: India, 2016.
Krambeck, R.H.; Lee, C.M.; Law, H.F.S. High-speed compact circuits with CMOS. IEEE J. Solid-State Circuits, 1982, 3, 614-619.
Heald, R. A third-generation SPARC V9 64-b microprocessor. IEEE J. Solid-State Circuits, 2000, 5, 1526-1538.
Suzuki, H.; Kim, C.H.; Roy, K. Fast tag comparator using diode partitioned domino for 64-bit microprocessors. IEEE Trans. Circ. Syst., 2007, 54, 322-328.
McEuen, P.L.; Fuhrer, M.S.; Park, H. Single-walled carbon nanotube electronics. IEEE Trans. NanoTechnol., 2002, 99, 78-85.
Fang, T.; Amine, B.; Zhouye, G. Low power dynamic logic circuit design using a pseudo dynamic buffer. Integr. VLSI J., 2012, 45, 395-404.
Mohammad, A. A new leakage-tolerant domino circuit using voltage comparison for wide fan-in gates in deep submicron technology. Integr. VLSI J., 2015, 51, 61-71.
Bansal, D.; Singh, B.P.; Kumar, A. Efficient keeper for pseudo domino logic. Int. J. Pure Appl. Math., 2017, 117, 605-612.
Alvandpour, A.; Krishnamurthy, R.; Sourrty, K.; Borkar, S.Y. A sub 130 nm conditional keeper technique. IEEE J. Solid-State Circuits, 2002, 37, 633-638.
Anis, M.H.; Allam, M.W.; Elmasry, M.I. Energy-efficient noise-tolerant dynamic styles for scale-down CMOS and MTCMOS technologies. IEEE Trans. VLSI Syst., 2002, 10, 71-78.
Lih, Y.; Tzartzanis, N.; Walker, K.K. A leakage current replica keeper for dynamic circuits. IEEE J. Solid-State Circuits, 2007, 42, 48-55.
Peiravi, A.; Asyaei, M. Robust low leakage controlled keeper by current-comparison for wide fan-in gates. IEEE Trans. VLSI Syst., 2012, 45, 22-32.
Dadoria, A.K.; Khare, K.; Panwar, U.; Jain, A. Performance evaluation domino logic circuits for wide fan-in gates with FinFET. Microsyst. Technol., 2018, 24(8), 3341-3348.
Palumbo, G.; Pennisi, M.; Alioto, M. A simple circuit approach to reduced delay variations in domino logic gates. IEEE Trans. Circ. Syst., 2012, 59, 2292-2300.
Kursun, V.; Friedman, E.G. Domino logic with variable threshold voltage keeper. IEEE Trans. VLSI Syst., 2003, 11, 1080-1093.
Mahmoodi, H.M.; Roy, K. Diode footed domino: A leakage-tolerant high fan-in dynamic circuit design style. IEEE Trans. Circ. Syst. I Fundam. Theory Appl., 2004, 51, 495-503.
Kao, J.T.; Chandrakasan, A.P. Dual threshold voltage techniques for low-power digital circuits. IEEE J. Solid-State Circuits, 2000, 35, 1009-1018.
Kursun, V.; Friedman, E.G. Sleep switch dual threshold voltage domino logic with reduced standby leakage current. IEEE Trans. VLSI Syst., 2004, 12, 485-496.
Shah, A.P.; Neema, V.; Daulatabad, S. DOIND: A technique for leakage reduction in nanoscale domino logic circuits. J. Semicond., 2016, 37, 055001-0550019.
Covino, J.J. Dynamic CMOS circuits with noise immunity. U.S. Patent 5650733,. 1997.
Evans, D.A. Noise-tolerant dynamic circuits. US Patent 5793228,. 1998.
Iijima, S. Helical microtubules of graphitic carbon. Nature 354,, 1991, 6348(1), 56-58.
Frueh, J.; Nakashima, N.; He, Q.; Möhwald, H. Effect of linear elongation on carbon nanotube and polyelectrolyte structures in PDMS-supported nanocomposite LbL films. J. Phys. Chem. B, 2012, 116(40), 12257-12262.
[] [PMID: 22978605]
Gai, M.; Kurochkin, M.A.; Li, D.; Khlebtsov, B.N.; Dong, L.; Tarakina, N.; Poston, R.; Gould, D.J.; Frueh, J.; Sukhorukov, G.B. In-situ NIR-laser mediated bioactive substance delivery to single cell for EGFP expression based on biocompatible microchamber-arrays. J. Control. Release, 2018, 276, 84-92.
[] [PMID: 29501723]
Gai, M.; Frueh, J.; Kudryavtseva, V.L.; Yashchenok, A.M.; Sukhorukov, G.B. Polylactic acid sealed polyelectrolyte multilayer microchambers for entrapment of salts and small hydrophilic molecules precipitates. ACS Appl. Mater. Interfaces, 2017, 9(19), 16536-16545.
[] [PMID: 28452456]
Sindeeva, O.A.; Gusliakova, O.I.; Inozemtseva, O.A.; Abdurashitov, A.S.; Brodovskaya, E.P.; Gai, M.; Tuchin, V.V.; Gorin, D.A.; Sukhorukov, G.B. Effect of a controlled release of epinephrine hydrochloride from PLGA microchamber array: In vivo studies. ACS Appl. Mater. Interfaces, 2018, 10(44), 37855-37864.
[] [PMID: 30299076]
Saha, P.; Jain, A.; Sarkar, S.K. Analytical modeling of read noise margin of a CNFET based 6T SRAM cell. Analog Integr. Circuits Signal Process., 2015, 83, 369-376.
Cen, M.; Song, S.; Cai, C. A high performance CNFET-based operational transconductance amplifier and its applications. Analog Integr. Circuits Signal Process., 2017, 91, 463-472.
Maleknejad, M.; Mirzaee, R.F.; Navi, K.; Naji, H.R. A capacitive multi-threshold threshold gate design to reach a high performance PVT-tolerant 4:2 compressor by carbon nanotube FETs. Analog Integr. Circuits Signal Process., 2018, 94, 233-246.
Stanford University, CNTFET Model Available at: http://nano.stanford. edu/model.php?id=232008.
Sun, Y.; Kursun, V. Carbon nanotubes blowing new life into NP dynamic CMOS circuits. IEEE Trans. Circ. Syst., 2014, 61, 420-428.

Rights & PermissionsPrintExport Cite as

Article Details

Year: 2020
Page: [58 - 67]
Pages: 10
DOI: 10.2174/1876402911666190716161631

Article Metrics

PDF: 17
PRC: 1