Design of Reversible Shift Register Using Reduced Number of Logic Gates

Author(s): Heranmoy Maity*, Sudipta Banerjee, Arindam Biswas, Anita Pal, Anup Kumar Bhattacharjee

Journal Name: Micro and Nanosystems

Volume 12 , Issue 1 , 2020

Become EABM
Become Reviewer
Call for Editor

Graphical Abstract:


Background: Over the last few decades, reversible logic system/circuits have received considerable attention in the diversified fields such as nanotechnology, quantum computing, cryptography, optical computing and low power design of VLSI circuits due to their low power dissipation characteristics.

Methods: In this paper, we proposed the design of reversible shift register (SR) i.e. serial-in-serial out (SISO), serial-in-parallel out (SIPO), parallel-in-serial out (PISO) and parallel-in-parallel out (PIPO) SR using a reduced number of reversible logic gates and garbage output.

Result: As compared to previously reported results, the improvement in our proposed model of SISO, SIPO, PISO and PIPO was found to be 50 – 66.66 %, 42.85 – 66.66 %, 12.5 – 53.33 % and 50 – 66.66 % respectively, in terms of the number of reversible logic gates.

Keywords: Reversible logic gate, flip-flop, delay, shift register, garbage output, VLSI.

Majid, H.; Navi, K. Novel reversible fault tolerant error coding and detection circuits. Int. J. Quant. Inf., 2011, 9, 723-738.
Maity, H.; Barik, A.K.; Biswas, A.; Bhattacharjee, A.K.; Pal, A. Design of quantum cost, garbage output and delay optimized BCD to excess-3 and 2’s complement code converter. J. Circuits Syst. Comput., 2018, 27(12)1850184
Maity, H.; Biswas, A.; Bhattacharjee, A.K.; Pal, A. Design of quantum cost efficient 4-bit reversible universal shift register. In: Proceeding of 2nd IEEE International Conference on Device for Integrated Circuits (DevIC 2017); Kalyani, India, 2017; pp. 44-47.
Feynman, R. Quantum mechanical computers. Optics News, 1985, 11, 11-20.
Majumder, A.; Singh, P.L.; Chowdhury, B.; Mondal, A.J.; Ananda, V. Efficient design and analysis of N-bit reversible shift registers. In: International Conference on Recent Trends in Computing 2015(ICRTC-2015); , 2015; pp. 199-208.
Ananthalakshmi, A.V.; Sudha, G.F. Design of 4-bit reversible shift registers. WSEAS Trans. Circ. Syst., 2013, 12, 376-385.
Nagapavani, T.; Rajmohan, V.; Rajendaran, P. Optimized shift register design using reversible logic. In: Proceedings of the 3rd IEEE International Conference on Electronics Computer Technology; Kanyakumari, India, 2011; pp. 236-239.
Maity, H.; Biswas, A.; Pal, A.; Bhattacharjee, A.K. Design of BCD to excess-3 code converter circuit with optimized quantum cost, garbage output and constant input using reversible gate. Int. J. Quant. Inf., 2018, 16(7)1850061
Thapliyal, H.; Ranganathan, N.; Kotiyal, S. Design of testable reversible sequential circuits. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems.,; , 2013; 21, pp. (7)1201-1209.
Ghose, P.; Rahman, M.N.; Polash, M.M.A.; Acharjee, U.K. Design of reversible shift registers minimizing number of gates, constant inputs and garbage outputs. In: Proceedings of International Conference on Advances in Computing, Communications and Informatics (ICACCI); Bangalore, India, 2018; pp. 752-758.

open access plus

Rights & PermissionsPrintExport Cite as

Article Details

Year: 2020
Page: [33 - 37]
Pages: 5
DOI: 10.2174/1876402911666190617112734

Article Metrics

PDF: 16
PRC: 1