Design of Reversible Shift Register Using Reduced Number of Logic Gates

Author(s): Heranmoy Maity*, Sudipta Banerjee, Arindam Biswas, Anita Pal, Anup Kumar Bhattacharjee

Journal Name: Micro and Nanosystems

Volume 12 , Issue 1 , 2020

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Graphical Abstract:


Background: Over the last few decades, reversible logic system/circuits have received considerable attention in the diversified fields such as nanotechnology, quantum computing, cryptography, optical computing and low power design of VLSI circuits due to their low power dissipation characteristics.

Methods: In this paper, we proposed the design of reversible shift register (SR) i.e. serial-in-serial out (SISO), serial-in-parallel out (SIPO), parallel-in-serial out (PISO) and parallel-in-parallel out (PIPO) SR using a reduced number of reversible logic gates and garbage output.

Result: As compared to previously reported results, the improvement in our proposed model of SISO, SIPO, PISO and PIPO was found to be 50 – 66.66 %, 42.85 – 66.66 %, 12.5 – 53.33 % and 50 – 66.66 % respectively, in terms of the number of reversible logic gates.

Keywords: Reversible logic gate, flip-flop, delay, shift register, garbage output, VLSI.

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Article Details

Year: 2020
Page: [33 - 37]
Pages: 5
DOI: 10.2174/1876402911666190617112734

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