An Accurate Drain Current Model for Symmetric Dual Gate Tunnel FET Using Effective Tunneling Length

Author(s): Sasmita Sahoo, Sidhartha Dash, Guru P. Mishra*

Journal Name: Nanoscience & Nanotechnology-Asia

Volume 9 , Issue 1 , 2019

Become EABM
Become Reviewer
Call for Editor

Graphical Abstract:


Introduction: Here we propose an accurate drain current model for a Symmetric Dual Gate Tunnel FET (SDG-TFET) using effective tunneling length and generation rate of carrier over tunneling junction area.

Analytical Modeling: The surface potential of the model is obtained by solving 2-dimensional Poisson’s equation and further extends to determine the magnitude of initial tunneling length and final tunneling length. The different DC performance indicators like drain current (ID), threshold voltage (Vth), transconductance (gm) and Subthreshold Slope (SS) for the present model are extensively investigated and the results are compared with that of Single Gate Tunnel FET (SGTFET).

Conclusion: The practical importance of this model relies on its accuracy and improved electrostatic performance over SG-TFET. The analytical model results are validated using TCAD Sentaurus (Synopsys) device simulator.

Keywords: Dual Gate Tunnel FET (DG-TFET), effective tunneling length, drain current, Symmetric Dual Gate Tunnel FET (SDGTFET), Subthreshold Slope (SS), Single Gate Tunnel FET (SG-TFET).

Colinge, J.P. Fin FETs and other Multi-Gate Transistors; Springer: New York, 2008.
Kumar, M.J.; Janardhanan, S. Doping-less tunnel field effect transistor: Design and investigation. IEEE Trans. Electron Dev., 2013, 60, 3285-3290.
Vishnoi, R.; Kumar, M.J. Compact analytical model of dual material gate tunneling field-effect transistor using interband tunneling and channel transport. IEEE Trans. Electron Dev., 2014, 61, 1936-1942.
Ghosh, B.; Akram, M.W. Junctionless tunnel field effect transistor. IEEE Electron Dev Lett., 2013, 34, 584-586.
Cui, N.; Liang, R.; Wang, J.; Xu, J. Si-based hetero-material-gate tun-nel field effect transistor: Analytical model and simulation. 12th IEEE International Conference on Nanotechnology (IEEE-NANO), 2012.
Ionescu, A.M.; Riel, H. Tunnel field-effect transistors as energy efficient electronic switches. Nature, 2011, 479, 329-337.
Pan, A.; Chen, S.; Chui, C.O. Electrostatic Modeling and Insights Re-garding Multigate Lateral Tunneling Transistors. IEEE Trans. Electron Dev., 2013, 60, 2712-2720.
Seabaugh, A.C.; Zhang, Q. Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE, 2010, 98, 2095-2110.
Choi, W.Y.; Park, B.G.; Lee, J.D.; Liu, T.J. Tunneling Field-effect Tran-sistors (TFETs) With Subthreshold Swing (SS) less than 60 mV/dec. IEEE Electron Dev Lett., 2007, 28, 743-745.
Biswas, A.; Dan, S.S.; Royer, C.L.; Grabinski, W.; Ionescu, A.M. TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model. Microelectron. Eng., 2012, 98, 334-337.
Lattanzio, L.; Biswas, A.; Michielis, L.D.; Ionescu, A.M. Abrupt switch based on internally combined band-to-band and barrier tunneling mechanisms. Solid-State Electron., 2011, 65, 234-239.
Kao, K.H.; Verhulst, A.S.; Vandenberghe, W.G.; Sorée, B.; Groesen-eken, G.; Meyer, K.D. Direct and indirect band-to-band tunneling in ger-manium-based TFETs. IEEE Trans. Electron Dev., 2012, 59, 292-301.
Trivedi, A.R.; Carlo, S.; Mukhopadhyay, S. Exploring tunnel-FET for ultra low power analog applications: A case study on operational trans-conductance amplifier. Automat. Conf, 2013, pp. 1-6.
Verhulst, A.N.; Sorée, B.; Leonelli, D.; Vandenberghe, W.G.; Groesen-eken, G. Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor. J. Appl. Phys., 2010, 107, 024518-1-10.
Gholizadeh, M.; Hosseini, S.E.A. 2-D analytical model for doublegate tunnel FETs. IEEE Trans. Electron Dev., 2014, 61, 1494-1500.
Dash, S.; Mishra, G.P. An extensive electrostatic analysis of dual mate-rial gate all around tunnel FET(DMGAA-TFET). Adv. Nat. Sci., 2016, 7, 025012-025021.
Dash, S.; Mishra, G.P. A 2D analytical cylindrical gate tunnel FET (CG-TFET) model: Impact of shortest tunneling distance. Adv. Nat. Sci., 2015, 6, 035005-035014.
Kumari, P.; Dash, S.; Mishra, G.P. Impact of technology scaling on analog and RF performance of SOI–TFET. Adv. Nat. Sci., 2015, 6, 045005-045014.
Bhushan, B.; Nayak, K.; Rao, V.R. DC compact model for SOI tunnel field-effect transistors. IEEE Trans. Electron Dev., 2012, 59, 2635-2642.
Shen, C.; Ong, S.L.; Heng, C.H.; Samudra, G.; Yeo, Y.C. A variation-al approach to the two-dimensional nonlinear Poisson’s equation for the modeling of tunneling transistors. IEEE Electron Dev Lett., 2008, 29, 1252-1255.
Lee, M.; Choi, W. Analytical model of single gate Silicon On Insulator (SOI) Tunnelling Field Effect Transistors (TFETs). Solid-State Electron., 2011, 63, 110-114.
Sentaurus Device User Guide; Synopsys, Inc.: Mountain View, USA, 2014.
Liu, L.; Mohata, D.; Datta, S. Scaling length theory of double-gate interband tunnel field-effect transistors. IEEE Trans. Electron Dev., 2012, 59, 902-908.
Yadav, M.; Bulusu, A.; Dasgupta, S. Two dimensional analytical mod-elling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: Potential and electric field. Microelectron J., 2013, 44, 1251-1259.
Huifang, X.; Yuehua, D.; Ning, L.; Jianbin, X.A. 2-D semi-analytical model of double-gate tunnel field-effect transistor. J. Semiconduc, 2015, 36, 054002-054008.
Chakraborty, A.; Sarkar, A. Investigation of analog/RF performance of staggered heterojunctions based nanowire tunneling field-effect transistors. Superlatt Microstruct., 2015, 80, 125-135.

Rights & PermissionsPrintExport Cite as

Article Details

Year: 2019
Published on: 26 December, 2018
Page: [85 - 91]
Pages: 7
DOI: 10.2174/2210681207666170612081017
Price: $25

Article Metrics

PDF: 21