Analytical Modeling of Threshold Voltage and Drain-Induced-Barrier- Lowering Variations Due to Gate Length Fluctuation in Nanometer MOSFETs

Author(s): Lu Weifeng*, Wang Guangyi, Lin Mi, Sun Lingling

Journal Name: Recent Advances in Electrical & Electronic Engineering
Formerly Recent Patents on Electrical & Electronic Engineering

Volume 10 , Issue 2 , 2017

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Graphical Abstract:


Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effecttransistors (MOSFETs), threshold voltage (VT) and drain-induced-barrier-lowering (DIBL) variations are regarded as significant challenges in circuit analysis, design and characterization.

Method: This paper proposes the improved analytical models to correctly describe VT and DIBL variations due to random gate length fluctuation employing the propagation of variation (POV) methodology.

Result: The presented models are validated that they can accurately capture VT and DIBL’s statistical characteristics through Monte Carlo simulations for MOSFET devices with 22nm process technology. Furthermore, our models and simulations both revealed that VT and DIBL variations will increase dramatically with gate length shrinking for nanometer MOSFETs.

Conclusion: The proposed statistical modeling approach provides a useful pathway for processvariation- aware circuit design.

Keywords: Analytical model, drain-induced-barrier-lowering, MOSFET device, nanometer MOSFET, process variation, threshold voltage.

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Article Details

Year: 2017
Published on: 12 September, 2017
Page: [128 - 133]
Pages: 6
DOI: 10.2174/1872212111666170530130424
Price: $25

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