Login Register Cart 0
Generic placeholder image

Nanoscience & Nanotechnology-Asia

Editor-in-Chief

ISSN (Print): 2210-6812
ISSN (Online): 2210-6820

Back
Journal Home About Journal Editorial Board Journal Insight Current Issue Volumes/Issues
Subscribe
Research Article

A Study on Sensitivity of Some Switching Parameters of JLT to Structural Parameters

Author(s): Subhro Ghosal*, Madhabi Ganguly and Debarati Ghosh

Volume 10, Issue 4, 2020

Page: [433 - 446] Pages: 14

DOI: 10.2174/2210681209666190905124818

Price: $65

Abstract

Background: The stringent technological constraints imposed by the requirement of ultra-sharp doping profiles associated with the sub-30 nm regime has led to the search for alternatives to the conventional Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET). An obvious alternative is a device whose architecture does not have any junctions in the sourcechannel- drain path. One such device is the Junctionless transistor comprising of an isolated ultrathin highly doped semiconductor layer whose volume is fully depleted in the OFF state and is around flat- band in the ON state. Such a structure overcomes the stringent technological requirement of an ultra-sharp grading profile required for nano-scale MOSFETs. For widespread application in today’s high-speed circuits, a key factor would be its effectiveness as a switch.

Methods: In this work we have studied the relative sensitivity of two such parameters namely the ION/IOFF ratio and gate capacitance to variations in several structural parameters of the device namely channel width, composition of the dielectric layer, material composition of the channel region (i.e. Si vis-à-vis SiGe), doping concentration of the channel region and non-uniformity in the doping profile.

Results: The work demonstrates through device simulations that replacement of Si with Si-Ge leads to an improvement in the performance.

Conclusion: The most notable change has been observed by using a vertically graded doping profile as opposed to the original proposed uniformly doped channel.

Keywords: JLT, ON/OFF ratio, dv/dt turn on, gate capacitance Si-Ge, variability, RDD.

Graphical Abstract

[1]
International Technology Roadmap for Semiconductors (ITRS). Available at: http://www.itrs.net
[2]
Skotnicki, T.; Merckel, G.; Pedron, T. The voltage-doping transformation: A new approach to the modeling of MOSFET short-channel effects. IEEE Electron Device Lett., 1988, 9, 109.
[http://dx.doi.org/10.1109/55.2058]
[3]
Barraud, S.; Berthomé, M.; Coquand, R.; Cassé, M.; Ernst, T.; Samson, M-P.; Perreau, P.; Bourdelle, K.K.; Faynot, O.; Poiroux, T. Scaling of trigate junctionless nanowire MOSFET with gate length down to 13 nm. IEEE Electron Device Lett., 2012, 33(9), 1225-1227.
[http://dx.doi.org/10.1109/LED.2012.2203091]
[4]
Colinge, J-P.; Lee, C-W.; Afzalian, A.; Akhavan, N.D.; Yan, R.; Ferain, I.; Razavi, P.; O’Neill, B.; Blake, A.; White, M.; Kelleher, A-M.; McCarthy, B.; Murphy, R. Nanowire transistors without junctions. Nat. Nanotechnol., 2010, 5(3), 225-229.
[http://dx.doi.org/10.1038/nnano.2010.15] [PMID: 20173755]
[5]
Colinge, J.P.; Lee, C.W.N. Akhavan, D.R. Yan, I.; Ferain, P.; Razavi, A.; Yu, R. Junctionless Transistors: Physics and Properties; Springer-Verlag: Berlin, Heidelberg, 2011.
[6]
Colinge, J-P.; Lee, C-W.; Ferain, I.; Akhavan, N.D.; Yan, R.; Razavi, P.; Yu, R.; Nazarov, A.N.; Doria, R.T. Reduced electric field in junctionless transistors. Appl. Phys. Lett., 2010, 96(7) 073510
[http://dx.doi.org/10.1063/1.3299014]
[7]
Han, M.; Chun, Y. Chen, h.; Cheng, Y.; Yung, C. Device and Circuit Performance Estimation of Junctionless Bulk FinFETs. IEEE Trans. Electron Dev., 2013, 60, 1807-1813.
[http://dx.doi.org/10.1109/TED.2013.2256137]
[8]
Sil, S.; Sil, M.; Mallik, A. Comparison of Logic performance of CMOS Circuits implemented with Junctionless and Inversion-Mode Fin-FETs. IEEE Trans. Electron Dev., 2017, 64(3), 953-959.
[http://dx.doi.org/10.1109/TED.2017.2655541]
[9]
Islam, S.; Afza, J.; Tarannum, S. Modelling and Performance Analysis of Asymmetric Double Gate Stack-Oxide Junctionless FET in Subthreshold Region. Int. J. Math. Comput. Simul., 2017, 1, 11.
[http://dx.doi.org/10.1109/R10-HTC.2017.8289017]
[10]
Kumar, S.; Kumar, S.; Gupta Karamveer, K.K.; Raj, B. Analysis of double gate dual material TFET device for low power SRAM cell design. Quantum Matter, 2016, (5), 762-766.
[11]
kumar, S.; kumar, S.; kumar, K.; Gupta, K.; Raj, B. Analysis of double gate dual material TFET device for low power SRAM cell design. Quantum Matter., 2016, 5, 762-766.
[http://dx.doi.org/10.1166/qm.2016.1381]
[12]
Park, H.; Dan, Y.; Seo, K.; Yu, Y.J.; Duane, P.K.; Wober, M.; Crozier, K.B. Filter-free image sensor pixels comprising silicon nanowires with selective color absorption. Nano Lett., 2014, 14(4), 1804-1809.
[http://dx.doi.org/10.1021/nl404379w] [PMID: 24588103]
[13]
Schupp, F.J. Single-electron devices in silicon. Mater. Sci. Technol., 2016, 33(8), 944-962.
[http://dx.doi.org/10.1080/02670836.2016.1242826]
[14]
Parihar, M.S.; Kranti, A. Enhanced sensitivity of double gate junctionless transistor architecture for biosensing applications. Nanotechnology, 2015, 26(14) 145201
[http://dx.doi.org/10.1088/0957-4484/26/14/145201] [PMID: 25771821]
[15]
Narang, R.; Saxena, M.; Gupta, M. Analytical modeling of a split-gate dielectric modulated metal-oxide-semiconductor field-effect transistor for application as a biosensor. Proceedings of the Devices IEEE Conference on Circuits and Systems (ICDCS), Combiatore, IndiaMarch 6-8, 2014
[16]
Chakraborty, A.; Sarkar, A. Analytical modeling and sensitivity analysis of dielectric-modulated junctionless gate stack surrounding gate MOSFET (JLGSSRG) for application as biosensor. J. Comput. Electron., 2017, 16(3), 556-567.
[http://dx.doi.org/10.1007/s10825-017-0999-2]
[17]
Rai, A.S. Reliability analysis of Junction-less Double Gate (JLDG) MOSFET for analog/RF circuits for high linearity applications. Microelectronics J., 2017, 64, 60-68.
[http://dx.doi.org/10.1016/j.mejo.2017.04.009]
[18]
Jegadheesan, V.; Sivasankaran, K. RF stability performance of SOI junctionless FinFET and impact of process variation. Microelectronics J., 2017, 59, 15-21.
[http://dx.doi.org/10.1016/j.mejo.2016.11.004]
[19]
Kumar, Sunil.Raj. B.; Estimation of stability and performance metric for inward access transistor based 6T SRAM cell design using n-type/p-type DMDG-GDOVTFET IEEE VLSI Circ. Syst. Lett, 2017, 3, 1.
[20]
Baruah, R.K.; Paily, R.P. A dual material double-layer gate stack junctionless transistor for enhanced analog performance. In: VLSI Design and Test; Springer: Berlin, Heidelberg, 2013.
[http://dx.doi.org/10.1007/978-3-642-42024-5_15]
[21]
Biswas, K.; Sarkar, A.; Sarkar, C.K. Effect of gate dielectrics on simulated device characteristics of nanoscale double gate heterostructure MOSFET. Adv. Indus. Eng. Manage, 2016, 5, 113-117.
[22]
Lee, B.H.; Kang, M.H.; Ahn, D.C.; Park, J.Y.; Bang, T.; Jeon, S.B.; Hur, J.; Lee, D.; Choi, Y.K. Vertically integrated multiple nanowire field effect transistor. Nano Lett., 2015, 15(12), 8056-8061.
[http://dx.doi.org/10.1021/acs.nanolett.5b03460] [PMID: 26544156]
[23]
Trevisoli, R.; De Souza, M.; Doria, R.T.; Kilchtyska, V.; Flandre, D.; Pavanello, M. Junctionless nanowire transistors operation at temperatures down to 4.2 K. Semicond. Sci. Technol., 2016. 31114001
[http://dx.doi.org/10.1088/0268-1242/31/11/114001]
[24]
Lin, J.Y.; Kuo, P.Y.; Lin, K.L.; Chin, C.C.; Chao, T.S. Junctionless Poly-Si nanowire transistors with low-temperature trimming process for monolithic 3-D IC application. IEEE Trans. Electron Dev., 2016, 63(12), 4998-5003.
[http://dx.doi.org/10.1109/TED.2016.2615805]
[25]
Doria, R.T.; Trevisoli, R.; De Souza, M.; Barraud, S.; Vinet, M.; Faynot, M. Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization. Microelectron. Eng., 2017, 1, 178.
[26]
Trevisoli, R.; Doria, R.T.; De Souza, M.; Pavanello, M. Modeling the interface trap density influence on junctionless nanowire transistors behavior. Proceedings of the IEEE SOI-3D-Subthreshold Microelectronics Technology Unified ConferenceBurlingame, CA, USAOctober 15-18, 2018
[27]
Sung, J.C.; Dong, M.; Sunghom, K.; Duarte, J.P.; Choi, Y.K. Sensitivity of threshold voltage to nanowire width variation in junctionless transistors. IEEE Electron Device Lett., 2011, 32(2), 125-127.
[http://dx.doi.org/10.1109/LED.2010.2093506]
[28]
Gnudi, A.; Reggiani, S.; Gnani, E.; Baccarani, G. Semi analytical Model of the subthreshold current in short- channel junctionless symmetric double-gate field-effect transistors. IEEE Trans. Electron Dev., 2013, 60(4), 1342-1348.
[29]
Ghosh, D.; Parihar, M.S.; Armstrong, G.A.; Kranti, A. High performance junctionless MOSFETs for ultralow- power analog/RF applications. IEEE Electron Device Lett., 2012, 33(10), 1477-1479.
[http://dx.doi.org/10.1109/LED.2012.2210535]
[30]
Atlas User’s Manual by Silvaco International.
[31]
Trevisoli, R.; Doria, R.; DeSouza, M. Threshold voltage in junctionless nanowire Transistors. Semicond. Sci. Technol., 2011, 26, 10.
[http://dx.doi.org/10.1088/0268-1242/26/10/105009]
[32]
Das, S.; Choudhury, A.; Ghosh, S.; Sarkar, S.; Chanda, M.; De, S. Parameter modeling of linearly doped double gate MOSFET with high-k dielectrics. Devices Integr. Circuit (DevIC), 2017, 1, 136-140.
[33]
Mallik, A.; Nawaz, M. Effects of device scaling on the performance of junctionless FinFETs due to gate-metal work function variability and random dopant fluctuations. IEEE Electron Device Lett., 2016, 37(8), 958-961.
[34]
Sharma, B.R.S.; Khosla, M. Subthreshold performance of In1-xGaxAs based dual metal with gate stack cylindrical/surrounding gate nanowire MOSFET for low power analog. J. Nanoelectron. Optoelectron, 2016, 11, 1-11.
[35]
Nawaz, M.; Dutta, S.; Mallik, A. A comparison of random discrete dopant induced variability between Ge and Si junctionless p- FinFETs. Appl. Phys. Lett., 2015, 107(3) 033506
[http://dx.doi.org/10.1063/1.4927279]
[36]
Kanungo, S.; Gupta, P.S.; Rhaman, H. Effects of Germanium mole fraction variation at the source of a dielectrically modulated Tunneling FET based biosensor. Proceedings of the 2nd International Conference on Devices, Circuits and Systems (ICDCS), Combiatore, IndiaMarch 6-8, 2014
[http://dx.doi.org/10.1109/ICDCSyst.2014.6926218]
[37]
Thompson, S.E.; Armstrong, M.; Auth, C.; Buchler, M. A 90-nm logic technology featuring strained-silicon. IEEE Trans. Electron Dev., 2004, 50, 1790.
[http://dx.doi.org/10.1109/TED.2004.836648]
[38]
Zhang, J.; Yuan, J.S.; Ma, Y. Modeling short channel effect on high-k and stacked-gate MOSFETs. Solid-State Electron., 2000, 44(11), 2089-2091.
[http://dx.doi.org/10.1016/S0038-1101(00)00152-0]
[39]
Zhao, D.D.; Lee, C.H.; Nishimura, T.; Nagashio, K.; Cheng, G.A.; Toriumi, A. Experimental and analytical characterization of dual-gated germanium junctionless p-channel metal–oxide–semiconductor field-effect transistors. Jpn. J. Appl. Phys., 2012, 51(4), 04DA03-1-04DA03-7.
[40]
Mondal, P.; Ghosh, B.; Bal, P. Planar junction less transistor with non-uniform channel doping. Appl. Phys. Lett., 2013, 102(13) 133505
[http://dx.doi.org/10.1063/1.4801443]
[41]
Liu, K.M.; Peng, F.I.; Peng, K.P.; Lin, H-C.; Huang, T.Y. The effects of channel doping concentration for n-typae junction-less double-gate poly-Si nanostrip transistors. Semicond. Sci. Technol., 2014, 29(5) 055001
[http://dx.doi.org/10.1088/0268-1242/29/5/055001]
[42]
Bal, P.; Ghosh, B.; Mondal, P.; Akram, M.W.A. A laterally graded junctionless transistor. J. Semicond., 2014, 35(3), 034001-034004.
[http://dx.doi.org/10.1088/1674-4926/35/3/034003]
[43]
Singh, B.; Gola, D.; Singh, K.; Goel, E.; Kumar, S.; Jit, S. Analytical modeling of channel potential and threshold voltage of double-gate junctionless FETs with a vertical gaussian-like doping profile. IEEE Trans. On. Electron Dev., 2016, 63(6), 2299-2305.
[http://dx.doi.org/10.1109/TED.2016.2556227]
[44]
Himangi, S.; Srivastava, V.M.; Singh, G. Performance analysis of undoped and Gaussian doped cylindrical surrounding-gate MOSFET with it’s small signal modeling. Microelectronics J., 2016, 57, 66-75.
[http://dx.doi.org/10.1016/j.mejo.2016.10.001]

Rights & Permissions Print Cite
Article Metrics
9
© 2024 Bentham Science Publishers | Privacy Policy