Performance Analysis of a Half Bridge Cell Based Asymmetrical Multilevel Inverter Topology with minimum components

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Author(s): Abeera Dutt Roy, Chandrahasan Umayal*.

Journal Name: Recent Advances in Electrical & Electronic Engineering
Formerly Recent Patents on Electrical & Electronic Engineering

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Background: In multilevel inverters(MLI) as the number of level increases, there is a proportionate increase in the count of the semiconductor devices that are employed.

Methods: This paper deals with an asymmetrical cascaded H-bridge inverter topology with half bridge cells to produce seven level output voltage waveform. Nearest level control(NLM) technique is used to produce the switching pulses. The operating principle of the proposed MLI and its performance abilities is verified through MATLAB/Simulink and a prototype is developed to provide the experimental results.

Results: Total Harmonic Distortion(THD) is computed for proposed MLI for different types of loads in simulation environment as well as in the developed hardware prototype. Comparison between the proposed MLI and recent topologies demonstrate the advantageous features.

Conclusion: The simulation and hardware results confirm the suitability of the proposed seven level MLI as the total component count and the requirement of DC sources reduces considerably.

Keywords: Cascaded H-bridge, THD, NLM, Asymmetrical, Half bridge, Conduction losses

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Article Details

(E-pub Ahead of Print)
DOI: 10.2174/2352096512666190417122807
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