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Nanoscience & Nanotechnology-Asia

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ISSN (Print): 2210-6812
ISSN (Online): 2210-6820

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Research Article

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

Author(s): Chiradeep Mukherjee*, Saradindu Panda, Asish K. Mukhopadhyay and Bansibadan Maji

Volume 10, Issue 4, 2020

Page: [534 - 547] Pages: 14

DOI: 10.2174/2210681209666190412142207

Price: $65

Abstract

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology.

Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc.

Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled.

Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

Keywords: QCA-based logic architectures, register, layered T gate, reliability, defect tolerance, cost analysis, logic optimization for QCA circuits.

Graphical Abstract

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