PVT Aware Design of a Dead-Zone Free High Speed Phase Frequency Detector in 90nm CMOS

(E-pub Ahead of Print)

Author(s): Suraj Kumar Saw, Madhusudan Maiti, Preetisudha Meher, Alak Majumder*.

Journal Name: Recent Advances in Electrical & Electronic Engineering
Formerly Recent Patents on Electrical & Electronic Engineering

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Background: With the advent of technology, though the literature highlights many designs of Phase Frequency Detector (PFD), there remains some challenges like area overhead, switching noise near frequency lock point and fast, accurate response to mitigate dead zone and output errors.

Objective: In this article, we have unearthed a low power, high speed and dead zone free PFD, which eliminates the switching noise near that lock-in node.

Methods: This simple design uses lesser number of transistors to obtain smaller estimated layout area of 0.748mm2 and low power of 496.12μW, when operated at 10 GHz frequency at a power supply of 1.8V in 90nm CMOS technology. The simulation reads a phase noise and output noise of -113.142dBc/Hz and -180.712dB at 1MHz offset. The circuit not only runs at a frequency as high as 40GHz, but also compatible to be operated at a power supply of as small as 0.9V.

Results: Process Variation analysis is performed to test the robustness of the proposed circuit at all process corners through Monte Carlo simulation.

Conclusion: Finally, the design is also validated at lower process nodes like 28nm UMC.

Keywords: Phase frequency detector, dead zone, Lock-in-time, Phase noise, Output noise

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Article Details

(E-pub Ahead of Print)
DOI: 10.2174/2352096512666190314111752
Price: $95

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