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Nanoscience & Nanotechnology-Asia

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ISSN (Print): 2210-6812
ISSN (Online): 2210-6820

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General Research Article

An Accurate Drain Current Model for Symmetric Dual Gate Tunnel FET Using Effective Tunneling Length

Author(s): Sasmita Sahoo, Sidhartha Dash and Guru P. Mishra*

Volume 9, Issue 1, 2019

Page: [85 - 91] Pages: 7

DOI: 10.2174/2210681207666170612081017

Price: $65

Abstract

Introduction: Here we propose an accurate drain current model for a Symmetric Dual Gate Tunnel FET (SDG-TFET) using effective tunneling length and generation rate of carrier over tunneling junction area.

Analytical Modeling: The surface potential of the model is obtained by solving 2-dimensional Poisson’s equation and further extends to determine the magnitude of initial tunneling length and final tunneling length. The different DC performance indicators like drain current (ID), threshold voltage (Vth), transconductance (gm) and Subthreshold Slope (SS) for the present model are extensively investigated and the results are compared with that of Single Gate Tunnel FET (SGTFET).

Conclusion: The practical importance of this model relies on its accuracy and improved electrostatic performance over SG-TFET. The analytical model results are validated using TCAD Sentaurus (Synopsys) device simulator.

Keywords: Dual Gate Tunnel FET (DG-TFET), effective tunneling length, drain current, Symmetric Dual Gate Tunnel FET (SDGTFET), Subthreshold Slope (SS), Single Gate Tunnel FET (SG-TFET).

Graphical Abstract

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