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Recent Patents on Electrical & Electronic Engineering


ISSN (Print): 2213-1116
ISSN (Online): 2213-1132

Optimizing IC Design for Manufacturability - 2011 Update

Author(s): Artur Balasinski

Volume 5 , Issue 2 , 2012

Page: [134 - 154] Pages: 21

DOI: 10.2174/2213111611205020134

Price: $65


Integrating Circuit Design for Manufacturability (IC DfM) involves various methodologies, techniques, and tools to improve semiconductor reliability and fab yield metrics by optimizing device design or layout. Recent years have seen propagation of IC DfM into the multiple aspects of semiconductor product definition. In addition to the traditional, mainstream DfM related to the corrections of circuit layout by the different types of pattern resolution enhancement techniques, recent DfM disclosures related to stacked die verification, 3D die packaging, floorplanning, and wiring have been proposed to help with the growing number of IC applications. These extended categories of DfM would be useful especially for Systems-on-Chip as well as for the further pursuit of IC shrinkability, e.g. by double patterning. In this work, we discuss nineteen representative IC DfM disclosures filed or published in 2011 and 2012. Similarly, as in the previous review [1], we divided the patents into the ones pertaining to DfM definition, DfM execution, and DfM verification. The focus of the first group of patents (definition) was the correct-by-construction (CBC) architecture, e.g., of layout (active devices, metal routing), die floorplan, or package. The second group (execution) pertained to process proximity correction (mostly OPC), and the third group (verification) concentrated on process model calibration and identifying the sources of process variability. These directions of DfM development, consistent over the recent years, show the validity of the existing DfM approach to solve future design problems.

Keywords: DfM, die packaging, floor planning, integrated circuit design, layout, OPC, process compensation, Correct-By-Construction

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