ESD Protection Design With Low-Capacitance Consideration for High-Speed/High-Frequency I/O Interfaces in Integrated Circuits

Title: ESD Protection Design With Low-Capacitance Consideration for High-Speed/High-Frequency I/O Interfaces in Integrated Circuits

Volume: 1 Issue: 2

Author(s): Ming-Dou Ker and Yuan-Wen Hsiao

Affiliation:

Keywords: Electrostatic discharge (ESD), input/output (I/O) interface, low capacitance (low-C), power-rail ESD clamp circuit, LC resonator, LC-tank, impedance cancellation, impedance isolation, impedance matching, distributed ESD protection scheme

Abstract: Electrostatic discharge (ESD) protection has been a very important reliability issue in microelectronics, especially for integrated circuits (ICs). ESD protection design for giga-Hz high-speed input/output (I/O) circuits has been one of the key challenges to implement high-speed interface circuits in CMOS technology. Conventional on-chip ESD protection circuits at the I/O pads often cause unacceptable performance degradation to high-speed I/O circuits. Therefore, ESD protection circuits must be designed with minimum negative impact to the high-speed interface circuits and to sustain high enough ESD robustness. In this paper, ESD protection design considerations for high-speed I/O circuits are addressed, and the patents related to on-chip ESD protection designs for high-speed I/O circuits are presented and discussed.

Cite this article as:

Ming-Dou Ker and Yuan-Wen Hsiao , ESD Protection Design With Low-Capacitance Consideration for High-Speed/High-Frequency I/O Interfaces in Integrated Circuits, Recent Patents on Engineering 2007; 1 (2) . https://dx.doi.org/10.2174/187221207780832174