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Recent Advances in Computer Science and Communications


ISSN (Print): 2666-2558
ISSN (Online): 2666-2566

General Research Article

Low Power and High Speed Sequential Circuits Test Architecture

Author(s): Ahmed K. Jameil*, Yasir A. Abbas and Saad Al-Azawi

Volume 14, Issue 5, 2021

Published on: 07 November, 2019

Page: [1669 - 1679] Pages: 11

DOI: 10.2174/2213275912666191107102512

Price: $65


Background: Electronic circuits testing and verification are performed to determine faulty devices after IC fabrication and to ensure that the circuit performs its designed functions. The verification process is considered as a test for both sequential and combinational logic circuits. The sequential circuits test is a more complex task than the combinational circuits test. However, dedicated algorithms can be used to test any type of sequential circuit regardless of its complexity.

Objective: This paper presents a new Design Under Test (DUT) algorithm for 4-and 8-tap Finite Impulse Response (FIR) filters sequential circuits. The FIR filter and the proposed DUT algorithm are implemented using field Programmable Gate Arrays (FPGA) platform.

Methods: The proposed DUT test generation algorithm is implemented using VHDL and Xilinx ISE V14.5 design suite. The proposed test generation algorithm for the FIR filter utilizes filtering redundant faults to obtain a set of target faults for the DUT.

Results: The proposed algorithm reduces time delay for up to 50 % with power consumption reduction of up to 70 % in comparison with the most recent similar work.

Conclusion: The implementation results ensured that a high speed and low power consumption architecture can be achieved. Also, the proposed architecture performance is faster than that of the existing techniques.

Keywords: Low power architecture, test generation algorithm, fault coverage, design under test, fault detection, FIR.

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