Design of Reconfigurable Architectures for Multi-Standards Video Decoder
Hua Z. Yang,
Digital video decoding is a typical data-intensive video processing application. Currently, high throughput and real time processing are the fundamental demands of performance for video processing systems. With the development of various video standards, multi-standard applications have become another key feature. Thus, the high performance, low area cost and low power consumption make up the most important design targets when realizing video processing chips. Reconfigurable hardware architectures have been reviewed in this paper, which could meet the above requirements for multi-standard video decoders. Traditional reconfiguration methods usually decrease area cost by reconfiguring the interconnections among function units. A relatively new approach is dynamic reconfiguration, which could reconfigure hardware resources at runtime. Recently, a new method called Reconfigurable Video Coding (RVC) has come up, which is a library-based method to design a reconfigurable system for multi-standard video decoders. An overview of the methodologies for reconfigurable video processing system is shown in the paper, as well as case studies, which demonstrate the effectiveness of the design flow. The article presents some promising patents on design of reconfigurable architectures for multi-standards video decoder.
Keywords: Reconfigurable hardware architecture, video decoder, multi-standard, dynamic reconfiguration, reconfigurable interconnection, reconfigurable video coding (RVC), real time processing, compressed video streams, real-time restriction, FPGA, ASIC implementation, System-on-Chip (SoC), granularities, runtime, coarse granularity, fine granularity, Multi-standard video encoding/decoding, bitstream, reconfigured modules, MPEG series, ISO, International Telecommunication Union (ITU), AVS, Audio Video coding Standard, H.26x series, Joint Video Team (JVT), high-density storage, resolution mobility, De-blocking Filter, interconnection reconfiguration, logic array reconfiguration, abstract system level, Library-based flow, dataflow graphs, CDDF, BDF, BDDF, token rate, synchronous dataflow, Dynamic Graph Topology (DGT), High Level Reconfiguration (HLR), Validation (VAL), Low Level Reconfiguration (LLR), reconfigurable IP cores, FU library, interconnection topology, syntax, semantics, MPEG-2/H.264 Dual-Standard Video Decoder, SystemC language, dual-standard decoder, Register Transfer Level (RTL), Hardware Description Language, behavior-level model, reference data reading, interpolation sub-modules, picture reconstruction, FIFO, DDR interface, header parser, inverse quantization, inverse transform, motion vector decoding and controller, QCIP video sequence decoding, RefRead
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