The level differences on the Printed Wiring Board (PWB) surface can keep the stencil away from the PWB during stencil printing, which causes large deposited solder paste volume, and can result in solder bridges after reflow soldering. The level differences can be caused by identity decals, or by other artifacts on the PWB. In our research the effect of these level differences on the deposited paste area and height were investigated. Test patterns were designed to have specific thickened surfaces formed by electroplating in continuously growing distance from soldering pads. Thus, there were intentional level differences on the test board between the soldering pads and the thickened surfaces. Three test boards were fabricated with level differences of 25, 55 and 90 μm. If these thickened surfaces were too close to the soldering pads then those surfaces kept away the stencil from the PWB during subsequent printing experiments. This simulates the effect of PWB decals and uneven solder mask thickness on Cu structures. With these test patterns we could investigate the stencil bending during the printing processes. After the printing experiments a Finite Element Method (FEM) model was created to determine the necessary distance which should be kept in order to achieve complete stencil contact to the PWB during the printing process. Different level differences (0-90 μm) were inserted into the FEM model as geometrical parameters, and simulations were executed for different stencil foil thicknesses (75-175 μm). The detailed results are presented in the paper.
Keywords: Printing process, solder deposit quality, solder paste, SMT technology, stencil bending, stencil printing, PWB, FEM, soldering pads, resistors, capacitors, Quad Flat Package, Ball Grid Array, CSPs, IPC-7525, STENCIL, TD, ASC Visionmaster, electroplating, 3D paste, pitch pads
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