Effective Memory Architectures of Multi-Processor Systems-on-Chip
Ni Zhou, Fei Qiao, Huazhong Yang and Hui Wang
Affiliation: Institute of Circuits and Systems, Dept. of Electronic Engineering, Tsinghua University, Beijing, P. R. China.
Keywords: Multi-Processor Systems-on-Chip (MPSoC), memory architecture, cache, scratch pad memory (SPM), Processor, semiconductor, (VLSI), DRAM, (OS), (SPM), (CMP), L1 Cache, L2 Cache, (PPE), (EIB), SPEs, (OpenMP), QoS, software, (RAP), (LPR), (MLP), (NB2CC), Architecture, (HAFF), (GVP), (DART), (ILP), Hardware design, Software design, GPU
MPSoC is becoming popular in all computing domains. However, the speed gap between processor and memory is increasing due to heavy access contention from multiple processors. Therefore, in MPSoC systems, one of the most critical components is memory systems, which dominate the speed, power, cost, and area. In order to narrow the gap and reduce the costs, two effective memory architectures are adopted in MPSoC-based platform architecture: cache-based and scratch-pad-memory-based architectures. Cache-based hierarchy, as a traditional technique, is widely employed in general-purpose systems. However, in embedded systems, to meet the rigorous power and cost constraints, scratch-padmemory- based architecture is preferred due to its flexibility and higher power efficiency. A short review is presented to introduce these two types of memory systems with some useful patents and researches in the field of MPSoC systems.
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