Heterogeneous Multi-core Systems for Video Processing
Multi-core system is the future of the embedded processor design for its power efficiency, multi-thread parallelization and flexibility. Meanwhile, with the improvement of the video processing algorithm, the processing capability requirement is also on the increase to meet such high processing capability requirement, the embedded multicore processor is developed as an appropriate choice. To better improve the performance of such systems, heterogeneous multi-core is preferred than homogeneous multi-core. For the design of such heterogeneous multi-core systems for video processing, the first and the most important step is to implement the system-level design and this paper gives an overview of such system-level design methodologies and some new methods for both cycle-approximate transaction-level modeling and cycle-accurate transaction-level modeling are given in detail. In addition, the system-level design framework for such systems is proposed and a case study of a heterogeneous multi-core h.264 video decoder shows that it can be used to design such systems effectively. The recent patents used for such designs are also listed accordingly.
Keywords: Heterogeneous multi-core, video processing, SystemC, instruction set simulator, multi-core, processing, instruction, power efficiency, flexibility, FPGA, Amadal's Law, NMR, DVFS, ISA, RTL-level, C-Models, ISS, LCC, SIMD, MPEG-1, MIPS, SSIAT, ISE
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