Patents in Power Analysis Attacks and their Countermeasures for Cryptographic Devices
Affiliation: School of Engineering, University of Guelph, Guelph, N1G 2W1, Canada.
Keywords: Side-channel attacks, power analysis attacks, differential power analysis attacks, countermeasures for power analysis attacks, current flattening technique, attacks, analysis attacks, differential, countermeasures, flattening, cryptographic devices, Encryption, decryption, DES, 3-DES, AES, RSA, ECC, TA, PAA, EME, DPA, (IC), CMOS, MOS, (A/D, S/N ratio, electromagnetic, desynchronization, SPA, VCC, IDD, ICC, (SABL), (DPDN), FPGA, RTL level, IP level
This paper presents an overview of security threats in cryptographic devices due to side-channel attacks. The mechanisms of power analysis attacks and their relationship to the underlying CMOS technology are considered. Specifically, differential power analysis is a statistical analysis attack that is successful in breaking the security of cryptographic devices, such as smart cards and even various embedded portable devices. The paper discusses the most significant patents related to the power analysis attacks mechanism and the most significant patents developed for the purpose of hardware based countermeasures against these attacks. The security of communication on all cryptographic devices is paramount and it is important to use the right techniques to accomplish the highest level of security.
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