Memory Reduction Techniques for HDTV Video Decoders
Hongli Gao, Fei Qiao, Huazhong Yang and Hui Wang
Affiliation: Institute of Circuits and Systems, Department of Electronic Engineering, Beijing, P.R. China.
Keywords: Memory reduction, frame storage architecture, memory management, HDTV video decoder, embedded compression, memory address translation
In the modern HDTV video decoding system, video frames must be stored into the external memory for operations of motion compensation and visual display. The massive data transferring between the decoder core and external memory contributes significantly to the overall system power consumption and bandwidth requirement. Practically, various memory reduction schemes are adopted to cope with this problem, which covers the domain of reducing the power consumption, desired memory size, and the number of Read/Write/Activate/Precharge operations of external memory. Embedded compression with less complexity, efficient frame storage architecture and improved memory management is the attractive strategy. The present review is a short review having some useful patents and researches is the field of memory reduction techniques in HDTV video decoder.
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