In this paper, a new technique is proposed for multiplication of two sampled analog signals and the result is in digital form. The analog signals which are to be multiplied are fed to the inputs of two different second order Delta sigma modulators after sampling at different sampling rates. The operating clock periods of the two DSMs are also different. The output of the DSM which is operating at higher clock frequency is inverted or not inverted depending on the bit state at the output of low frequency DSM. The resulting bit stream at the output of multiplier is the digital representation of the product of the two analog signals. Most important patents are also discussed in this article.
Keywords: DSM based multiplier, sample and hold circuit, sampling period, error signal
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