Galois Field Inversion/Division Using Multiple-Valued Logic
We present a pipelined inversion/division circuit in Galois field using AB2 circuit technique (where both A and B are elements in the finite field). We use composite Galois fields in a multiple-valued logic (MVL) approach to minimize the inversion/division circuit needed for binary Galois fields. The overall design, which connects basic cells in a systolic manner, thereby making effective use of pipelining, is shown. The fact that less literals are used speeds up the calculation operation. Also, our circuit shows a significant amount of savings in both transistor count and connections, which is so important in VLSI. In this review important patents are also discussed.
Keywords: MVL, galois field, inversion/division
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