Optimizing IC Design for Manufacturability
Affiliation: Cypress Semiconductor, 12230 World Trade Drive, San Diego, CA 92129, USA.
Keywords: Integrated circuit design, layout, yield, hot spots, manufacturing, models, cell design, die verification
Design for Manufacturability (DfM) improves semiconductor integrated circuit (IC) yield by optimizing product design or layout. Positive impact of DfM on yield can be realized at production time (e.g., parametric yield), at the end of production (e.g., functional yield), or in the field (e.g., reliability yield). Patents issued in 2007-2008 timeframe enhance DfM in all these domains. In this paper, we review examples of DfM patent coverage starting from the new correct-by-construction layout concepts for single cells, extending into multi-cell intellectual property (IP) and mask level. Another DfM patent family proposes new design verification techniques by which the manufacturing delivers feedback to design/layout e.g., to remove local yield limiters (hot spots). The new concepts involve EDA algorithms, computer programs, and design kits, which help optimize the DfM related modifications of the layout. A number of patents improve the way design or layout corrected by DfM is verified by inspection or simulation, before a mask set is built. They also address DfM data collection, storage, and transfer to improve communication and cross-fab compatibility, when the same mask set is delivered to different manufacturers or comes from different design houses, with important aspects of data protection and cost reduction.
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