Automatic High-Level Code Generation for Multi-Core Processors in Embedded Systems
Pp. 78-92 (15)
Yu-Shin Lin, Shang-Wei Lin, Chao-Sheng Lin, Chun-Hsien Lu, Chia-Chiao Ho, Yi-Luen Chang, Bo-Hsuan Wang and Pao-Ann Hsiung
This chapter demonstrates how high-level code is automatically generated for multi-core processors.
The code generation capability of the Verifiable Embedded Real-Time Application Framework (VERTAF) was
extended to support multi-core processors in the new VERTAF/Multi-Core (VMC) framework for embedded
systems. After users specify embedded software requirements via SysML models along with parallel task, parallel
data, and parallel dataflow specifications, the code generator automatically generates parallel code. Using the
digital video recording (DVR) system as a case study, we show the correctness and advantages of the VMC code
generator. The main inputs of VMC code generator include the block definition diagrams, state machine
diagrams, and requirement diagrams of the system to be designed. The proposed code generation in VMC not
only significantly decreases the amount of manually-written code, but also provides a formal procedure for
model-conforming code generation of multi-core embedded software.
Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi-62102, Taiwan, ROC.