Multicore Hardware-Software Design and Verification Techniques

Indexed in: Scopus, EBSCO.

The surge of multicore processors coming into the market and on users’ desktops has made parallel computing the focus of attention once again. This time, however, it is led by the industry, which ...
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TRoCMP: An Approach to Energy Saving for Multi-Core Systems

Pp. 33-60 (28)

Long Zheng, Mianxiong Dong, Minyi Guo, Song Guo, Kaoru Ota and Jun Ma


Nowadays, multi-core processor, also called Chip Multiprocessor (CMP) becomes the mainstream that can achieve higher computation capability. However, energy issue is still a crucial problem for design and manufacture of multi-core processor. Tag reduction technique can save energy of the single-core system. This chapter introduces the Tag Reduction on CMP (TRoCMP) that is a novel approach to energy saving for multicore system. We first extend tag reduction from single-core to multi-core processor, including proposing 3 heuristic algorithms to implement TRoCMP. Then the performance overhead is considered, so that Core Degree mechanism and a refined heuristic algorithm are further introduced and designed to find out the trade-off of energy saving and performance overhead of TRoCMP. In particular, we formulate the energy consumption and performance overhead of TRoCMP to analyze and estimate them. In experiments, we modify the Linux kernel and implement new modules to collect the experimental data from benchmarks of SPEC CPU2006 running on a real operating system. In this way, the precision of our experiments is guaranteed, since tag reduction is very sensitive to the usage of physical memory. The experimental results show that our TRoCMP can save total energy up to 83.93% and 76.16% on 8-core and 4-core processors in average respectively, compared to the one that the tag-reduction is not used for. TRoCMP outperforms significantly tag reduction on single-core processor as well. With consideration of performance overhead, when Core Degree is set to 6, the best balance of energy saving and performance overhead can be achieved.


1School of Computer Science and Engineering, University of Aizu, Aizu-Wakamatsu, 965-8580, Japan.