Recent Topics on Modeling of Semiconductor Processes, Devices, and Circuits

Indexed in: Scopus, EBSCO.

The last couple of years have been very busy for the semiconductor industry and researchers. The rapid speed of production channel length reduction has brought lithographic challenges to ...
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Chip-Level Statistical Leakage Modeling and Analysis

Pp. 120-148 (29)

Sheldon X.-D. Tan and Ruijing Shen

Abstract

This chapter reviews the recent chip-level statistical leakage power analysis methods. We first show main sources of leakage from a chip, which consists of three main components: subthreshold leakage, gate oxide leakage and junction tunnelling leakage. We then study the leakage variational models and show that one needs to consider both intra-die and inter-die variations with spatial correlations. Then we review recently proposed statistical leakage analysis methods. These methods include the Monte-Carlo based method, the grid-based method, the gate-based spectral stochastic method and the projection-based method. Brief descriptions, as well as the advantages and disadvantages of these methods are also presented in this chapter. Numerical examples are further provided to give quantitative comparisons among these methods.

Affiliation:

Department of Electrical Engineering University of California at Riverside Riverside, CA 92521