Recent Topics on Modeling of Semiconductor Processes, Devices, and Circuits

Indexed in: Scopus, EBSCO.

The last couple of years have been very busy for the semiconductor industry and researchers. The rapid speed of production channel length reduction has brought lithographic challenges to ...
[view complete introduction]

US $
15

*(Excluding Mailing and Handling)



Compact Modeling of Engineered Strain

Pp. 81-119 (39)

Richard Q. Williams

Abstract

Engineered strain, or the inclusion of Ultra Large-Scale Integration (ULSI) process technology that intentionally modifies channel strain in a metal-oxide-semiconductor field-effect transistor (MOSFET), is now a common component of high-performance logic chips. Beneficial channel strain physically deforms the crystal lattice and alters the crystal energy band structure, enhancing carrier transport. This transport enhancement can be a significant contributor to the performance uplift in a ULSI technology node-to-node transition.

A side effect of engineered strain is that the physical mechanisms that introduce strain in a MOSFET are affected by the types and dimensions of the physical structures in the MOSFET’s immediate vicinity. Analysis of strain layout dependency is in general a complex three-dimensional problem, however it can be reduced to compact model-compatible form so that circuit designers can evaluate its impact on circuit response. This chapter reviews recent technology, physics, characterization techniques, modeling approaches, and simulation literature in the field of engineered strain compact modeling.

Affiliation:

IBM Semiconductor Research and Development Center 1000 River Road, Essex Junction, Vermont 05452