Recent Topics on Modeling of Semiconductor Processes, Devices and Circuits

Indexed in: Scopus, EBSCO.

The last couple of years have been very busy for the semiconductor industry and researchers. The rapid speed of production channel length reduction has brought lithographic challenges to ...
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Probability Propagation and Yield Optimization for Analog Circuits

Pp. 61-80 (20)

Rasit O. Topaloglu, Guo Yu and Peng Li

Abstract

Monte Carlo analysis has so far been the corner stone for analog statistical simulations. Fast and accurate simulations are necessary for stringent time-to-market, design for manufacturability and yield concerns in the analog domain. Although Monte Carlo attains accuracy, it does so with a sacrifice in run-time for analog simulations. In this chapter, we propose a fast and accurate probabilistic simulation method alternative to Monte Carlo using deterministic sampling and weight propagation. We furthermore propose accuracy improvement algorithms and a fast yield calculation method. The proposed method shows accuracy improvement combined with a 100-fold reduction in run-time with respect to a 1000 sample Monte Carlo analysis.

Hierarchical optimization using circuit block Pareto performance models is an efficient and well established approach for optimizing the nominal performances of large analog circuits. However, the extension to yield-aware hierarchical methodology, as dictated by the need for safeguarding chip manufacturability in scaled technologies, is completely nontrivial. We address two fundamental difficulties in achieving such a methodology: yield-aware Pareto performance characterization at the building block level and yield-aware system-level optimization problem formulation. It is shown that our approach is not only able to effectively capture the block performance trade-offs at different yield levels, but also correctly formulate the whole system yield and efficiently perform system-level optimization in presence of process variations. Our approach extends the efficiency of hierarchical analog optimization, improving nominal circuit performance metrics towards yield-aware optimization. Our methodology is demonstrated by the hierarchical optimization of a phase-locked loop (PLL) consisting of multiple circuit blocks.

Affiliation:

GLOBALFOUNDRIES, USA