Design Techniques for Power-Gated Nanoscale Low Power Circuits

(E-pub Ahead of Print)

Author(s): Rumi Rastogi, Sujata Pandey*, Mridula Gupta.

Journal Name: Micro and Nanosystems

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Abstract:

Background: With the shrinking device-sizes in present day world, the leakage power of the devices has also increased significantly. Several techniques have been proposed to minimize the leakage power. But the techniques suffer from drawbacks such as noise, delay or area of the chip. We have also proposed a leakage minimization technique which also minimizes the noise in the circuit.

Objective: In this paper we propose noise minimization circuit techniques for the distributed sleep transistor network in power-gated Multi-threshold CMOS circuits. The objective is to minimize leakage power as well as the noise associated with digital power-gated circuits.

Method: The proposed technique has been verified through simulations using the Cadence virtuoso tool. The proposed technique has been applied to a 16-bit adder circuit in 45 nm MTCMOS technology.

Results: The proposed techniques i.e. HVT-ST and the Hybrid-ST techniques achieve 99%, 64.8% and 62.07% reduction in noise as compared to the All-ON, variable-width and variable gate-voltage techniques respectively. The behaviour of the circuit techniques have also been analyzed at higher temperatures. It has been shown through simulations that the proposed techniques effectively minimize noise at higher temperatures i.e. 75°C and 115°C. The proposed techniques also minimizes leakage power and the on-time delay significantly. A layout of a section of the proposed circuit has also been drawn which occupies chip area of 2.37µm2.

Conclusion: The proposed techniques i.e. HVT-ST and the Hybrid-ST techniques achieve significant reduction in noise as well as delay. Our proposed techniques achieve 99%, 64.8% and 62.07% reduction in noise as compared to the All-ON, variable-width and variable gate-voltage techniques respectively. The behaviour of the circuit techniques have also been evaluated at higher temperatures.

Keywords: Distributed sleep transistor Network, HVT-ST, Hybrid ST, MTCMOS, Variable-width, HVT- ST, Hybrid-ST

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Article Details

(E-pub Ahead of Print)
DOI: 10.2174/1876402911666190405122417