Background: The Adder is one of the most prominent building blocks in VLSI circuits and systems. Performance of such systems depends mostly on the performance of the adder cell. The scaling down of devices has been the driving force in technological advances. However, in CMOS technology performance of adder cell decreases as technology node scaled down to deep micron regime.
Objective: With growth of research, new device model has been proposed based on ‘carbon nano tube field effect transistor’ (CNFET). Therefore, there is a need of full adder cell, which perform sufficiently well in CNFET as well as different CMOS technology nodes.
Method: A new low power full adder cell has been proposed with a hybrid XOR/XNOR module by using CNFET, which is also compatible for CMOS technology nodes. The performance of the adder cell is validated with HSPICE simulation in terms of power, delay and power delay product. It is observed that the proposed adder cell performs better than those CMOS, CPL, TGA, 10T, 14T, 24T, HSPC and Hybrid_FA adder cells. The CNFET full adder is designed in 32nm CNFET model and to appraise it’s compatibility with Bulk-Si CMOS technology, 90nm and 32nm CMOS technology node is used.
Conclusion: The proposed adder is very much suitable for both CMOS and CNFET technology based circuits and systems. To validate the result, simulation has been carried out with Synopsis tool. This full adder will definitely dominate other full adder cells at various technology nodes for VLSI applications.