Background: This work describes the implementation of In0.53Ga0.47As/InP Surrounding
Metal Gate Oxide Semiconductor Heterostructure Field Effect Transistor (SG MOSHFET)
with gate underlap on both source and drain end to improve the DC and RF performance.
Methods: A comprehensive and methodological investigation of DC and RF performance of III-V
semiconductor are made for different underlap length varying from 5nm to 30nm on both sides of
the device, which is used to mitigate the short channel issues to improve the device performance.
Hydrodynamic model has been taken into consideration for the device simulation and it also includes
Auger recombination and the Shockley–Read–Hall (SRH) model. Simulation is performed
to analyze the various analog performance of device like drain current, surface potential, transconductance,
threshold voltage, drain induced barrier lowering, off current, subthreshold slope,
Ion/Ioff ratio, output conductance, intrinsic delay, energy-delay product, transconductance generation
factor and radio frequency performance of device, like trans-frequency product and cut-off
Results: From the simulation, it can be observed that an improved analog and RF performance is
obtained at the optimum underlap length.
Conclusion: This work delivers an idea for extended researchers to investigate different aspects of
group III–V underlap MOSFETs.