Background: A hydrogen-based Ion-Cut layer-transfer technique, the so-called Ion-Cut or
Smart-Cut processing, has been used in transferring a semiconductor membrane onto a desired substrate
to reveal unique characteristics on a nanoscale size and to build functional electronic and photonic devices
that are used for specific purposes. For example, the sub-100 nm thick silicon membrane transferred
onto an insulator became a key substrate for fabricating nanoscale integrated circuit (IC) devices.
Recent U.S. patents have exhibited integration of various thinning approaches requiring precision of a
few nanometers in fabricating large-area semiconductor nanomembranes, especially for silicon. This
paper reviews published patents and work on fabricating sub-100 nm silicon membranes with welldefined
features without a chemical-mechanical polishing (CMP) thinning process. This included material
analysis leads to ultraprecision thickness in the sub-100 nm region.
Methods: This paper combines an analysis of peer-reviewed articles and issued patents using focused
review keywords of hydrogen implantation, wafer bonding, and layer splitting. The quality of selected
patents was appraised based on the authors’ 20-year research experience in the field of ultrathin silicon
Results: The paper covered more than 10 U.S. patents that have been filed on hydrogen-based Ion-Cut
layer-transfer techniques. These patents described approaches for inserting hydrogen ions to split at a
well-defined location and then transfer the as-split silicon membrane at the nanoscale thickness onto a
desired substrate. Hydrogen-trap sites, implantation energy, and interface of the distinct doped regions
could define the layer-split location. The insertion of high-dose hydrogen ions could be thoroughly
achieved by ion implantation, plasma ion immersion implantation (PIII), plasma diffusion, and electrolysis.
Conclusion: The article concludes with the discussion of the patent-orientated review of layer-transfer
techniques and makes some concrete suggestions for manufacturing the FDSOI substrate, the key material
technology to fabricate nanoscale microelectronics for applications in artificial intelligence for