Recent Architectural Developments for Reducing Power Consumption and Increasing Performance

Author(s): Tarik Ozkul, Mohammed A. Tuffaha, Lamees Elhiny.

Journal Name: Recent Patents on Computer Science

Volume 9 , Issue 1 , 2016

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Background: Power consumption has become one of the most serious obstacles ahead of performance increase. Due to increased power consumption, increasing number of transistors does not seem to be viable anymore. We are being forced to consider other ways of increasing performance without increasing power consumption. To fınd solution to the problem, the power consumption issue is being looked at more and more carefully at architectural level.

Methods: Recent publications and patent databases are reviewed to find extraordinary and innovative architectural techniques developed for reducing power consumption and increasing performance.

Results: In most of the cases the focus was specifically on memory area because of the studies that indicated that memory is the biggest power consumer in a typical processor system. The focus of the most methods was also on the cache memory part of the processor system since cache memory is a part that is used with every instruction execution. Any reduction in power cost of the cache memory results in sizable power reduction. Among the methods suggested were techniques of linking cache memory cells to reduce number of operations, reducing size of the cache memory by using multiple small cache memories activated one at a time.

Conclusion: Based on the study it can be concluded that future innovative developments to reduce power consumption should concentrate on: a) Main memory part: to reduce the power consumption of main memory by turning on/off unused blocks of memory without effecting performance, b) Cache memory part: use of cache memory efficiently without decreasing performance, c) Efficient multiprocessing architectures. By integrating above mentioned methods to multiprocessors it may be possible to reduce the power consumption further.

Keywords: Instruction Set Architecture (ISA), power, Register File (RF), Register lock, multiprocessing, linked cache, one bit tagged cache, code compression, shared resources.

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Article Details

Year: 2016
Page: [89 - 98]
Pages: 10
DOI: 10.2174/2213275908666150706175833

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PDF: 17