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A Model to Improve Analysis of CNTFET Logic Gates in Verilog-A-Part I: Static Analysis

Author(s): Gennaro Gelao, Roberto Marani, Luciano Pizzulli, Anna Gina Perri.

Graphical Abstract:


Abstract:

In this paper we have implemented a simple DC model for CNTFETs already proposed by us in order to carry out static analysis of basic digital circuits, with a significant improvement compared to Wong model. In particular we have obtained a lighter ensuring compile and shorter execution time, without losing in accuracy.

Keywords: CNTFETs modelling, digital applications, noise margin, sub threshold currents.

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Article Details

VOLUME: 11
ISSUE: 4
Year: 2015
Page: [515 - 526]
Pages: 12
DOI: 10.2174/1573413711666150320231414
Price: $58