A Model to Improve Analysis of CNTFET Logic Gates in Verilog-A-Part I: Static Analysis
Anna Gina Perri.
In this paper we have implemented a simple DC model for CNTFETs already proposed by
us in order to carry out static analysis of basic digital circuits, with a significant improvement compared
to Wong model. In particular we have obtained a lighter ensuring compile and shorter execution
time, without losing in accuracy.
Keywords: CNTFETs modelling, digital applications, noise margin, sub threshold currents.
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